Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
802
remains active. To de-assert the chip select line at the end of the transfer, the Last Transfer (LASTXFER) bit in the
SPI_MR must be set to 1 before writing the last data to transmit into the SPI_TDR.
SPI_MR must be set to 1 before writing the last data to transmit into the SPI_TDR.
35.7.3.10 Peripheral Deselection with DMA or PDC
DMA or PDC provides faster reloads of the SPI_TDR compared to software. However, depending on the system
activity, it is not guaranteed that the SPI_TDR is written with the next data before the end of the current transfer.
Consequently, a data can be lost by the de-assertion of the NPCS line for SPI slave peripherals requiring the chip
select line to remain active between two transfers. The only way to guarantee a safe transfer in this case is the use
of the CSAAT and LASTXFER bits.
activity, it is not guaranteed that the SPI_TDR is written with the next data before the end of the current transfer.
Consequently, a data can be lost by the de-assertion of the NPCS line for SPI slave peripherals requiring the chip
select line to remain active between two transfers. The only way to guarantee a safe transfer in this case is the use
of the CSAAT and LASTXFER bits.
When the CSAAT bit is configured to 0, the NPCS does not rise in all cases between two transfers on the same
peripheral. During a transfer on a Chip Select, the TDRE flag rises as soon as the content of the SPI_TDR is
transferred into the internal shift register. When this flag is detected, the SPI_TDR can be reloaded. If this reload
occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the
current transfer, the Chip Select is not de-asserted between the two transfers. This can lead to difficulties to
interface with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate
interfacing with such devices, the SPI_CSR can be programmed with the Chip Select Not Active After Transfer
(CSNAAT) bit to 1. This allows the chip select lines to be de-asserted systematically during a time “DLYBCS” (the
value of the CSNAAT bit is processed only if the CSAAT bit is configured to 0 for the same chip select).
peripheral. During a transfer on a Chip Select, the TDRE flag rises as soon as the content of the SPI_TDR is
transferred into the internal shift register. When this flag is detected, the SPI_TDR can be reloaded. If this reload
occurs before the end of the current transfer and if the next transfer is performed on the same chip select as the
current transfer, the Chip Select is not de-asserted between the two transfers. This can lead to difficulties to
interface with some serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate
interfacing with such devices, the SPI_CSR can be programmed with the Chip Select Not Active After Transfer
(CSNAAT) bit to 1. This allows the chip select lines to be de-asserted systematically during a time “DLYBCS” (the
value of the CSNAAT bit is processed only if the CSAAT bit is configured to 0 for the same chip select).
shows different peripheral deselection cases and the effect of the CSAAT and CSNAAT bits.