Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
804
35.7.4 SPI Slave Mode
When operating in Slave mode, the SPI processes data bits on the clock provided on the SPI clock pin (SPCK).
The SPI waits until NSS goes active before receiving the serial clock from an external master. When NSS falls, the
clock is validated and the data is loaded in the SPI_RDR depending on the BITS field configured in the SPI_CSR0.
These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits in
the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select registers have no effect when the SPI
is programmed in Slave mode.
clock is validated and the data is loaded in the SPI_RDR depending on the BITS field configured in the SPI_CSR0.
These bits are processed following a phase and a polarity defined respectively by the NCPHA and CPOL bits in
the SPI_CSR0. Note that BITS, CPOL and NCPHA of the other Chip Select registers have no effect when the SPI
is programmed in Slave mode.
The bits are shifted out on the MISO line and sampled on the MOSI line.
Note:
For more information on the BITS field, see also the note below the SPI_CSRx register bitmap (
).
When all bits are processed, the received data is transferred in the SPI_RDR and the RDRF bit rises. If the
SPI_RDR has not been read before new data is received, the Overrun Error Status (OVRES) bit in the SPI_SR is
set. As long as this flag is set, data is loaded in the SPI_RDR. The user must read SPI_SR to clear the OVRES bit.
SPI_RDR has not been read before new data is received, the Overrun Error Status (OVRES) bit in the SPI_SR is
set. As long as this flag is set, data is loaded in the SPI_RDR. The user must read SPI_SR to clear the OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift register. If no data has been written in
the SPI_TDR, the last data received is transferred. If no data has been received since the last reset, all bits are
transmitted low, as the Shift register resets to 0.
the SPI_TDR, the last data received is transferred. If no data has been received since the last reset, all bits are
transmitted low, as the Shift register resets to 0.
When a first data is written in the SPI_TDR, it is transferred immediately in the Shift register and the TDRE flag
rises. If new data is written, it remains in the SPI_TDR until a transfer occurs, i.e., NSS falls and there is a valid
clock on the SPCK pin. When the transfer occurs, the last data written in the SPI_TDR is transferred in the Shift
register and the TDRE flag rises. This enables frequent updates of critical variables with single transfers.
rises. If new data is written, it remains in the SPI_TDR until a transfer occurs, i.e., NSS falls and there is a valid
clock on the SPCK pin. When the transfer occurs, the last data written in the SPI_TDR is transferred in the Shift
register and the TDRE flag rises. This enables frequent updates of critical variables with single transfers.
Then, a new data is loaded in the Shift register from the SPI_TDR. If no character is ready to be transmitted, i.e. no
character has been written in the SPI_TDR since the last load from the SPI_TDR to the Shift register, the
SPI_TDR is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in the SPI_SR.
character has been written in the SPI_TDR since the last load from the SPI_TDR to the Shift register, the
SPI_TDR is retransmitted. In this case the Underrun Error Status Flag (UNDES) is set in the SPI_SR.
shows a block diagram of the SPI when operating in Slave mode.
Figure 35-12. Slave Mode Functional Block Diagram
Shift Register
SPCK
SPIENS
LSB
MSB
NSS
MOSI
SPI_RDR
RD
SPI
Clock
TDRE
SPI_TDR
TD
RDRF
OVRES
SPI_CSR0
CPOL
NCPHA
BITS
SPIEN
SPIDIS
MISO