Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

803

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The SPI has the capability to operate in multi-master environment. Consequently, the NPCS0/NSS line must be
monitored. If one of the masters on the SPI bus is currently transmitting, the NPCS0/NSS line is low and the SPI
must not transmit a data. A mode fault is detected when the SPI is programmed in Master mode and a low level is
driven by an external master on the NPCS0/NSS signal. In multi-master environment, NPCS0, MOSI, MISO and
SPCK pins must be configured in open drain (through the PIO controller). When a mode fault is detected, the
MODF bit in the SPI_SR is set until SPI_SR is read and the SPI is automatically disabled until it is re-enabled by
writing a 1 to the SPIEN bit in the SPI_CR.

By default, the mode fault detection is enabled. The user can disable it by setting the MODFDIS bit in the SPI_MR. 

A

NPCS[0..n]

Write SPI_TDR

TDRE

NPCS[0..n]

Write SPI_TDR

TDRE

NPCS[0..n]

Write SPI_TDR

TDRE

DLYBCS

PCS = A

DLYBCS

DLYBCT

A

PCS = B

B

DLYBCS

PCS = A

DLYBCS

DLYBCT

A

PCS = B

B

DLYBCS

DLYBCT

PCS=A

A

DLYBCS

DLYBCT

A

PCS = A

A

A

DLYBCT

A

A

CSAAT = 0 and CSNAAT = 0

DLYBCT

A

A

   

CSAAT = 1 and CSNAAT= 0 / 1 

A

DLYBCS

PCS = A

DLYBCT

A

A

CSAAT = 0 and CSNAAT = 1

NPCS[0..n]

Write SPI_TDR

TDRE

PCS = A

DLYBCT

A

A

CSAAT = 0 and CSNAAT = 0