Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

These bits must be written to 0x0 or 0x1 to select the USART serial communication interface of the SERCOM.

0x0: USART with external clock.

0x1: USART with internal clock.

These bits are not synchronized.

z

Bit 1 – ENABLE: Enable
0: The peripheral is disabled or being disabled.

1: The peripheral is enabled or being enabled.

Due to synchronization, there is delay from writing CTRLA.ENABLE until the peripheral is enabled/disabled. The 
value written to CTRLA.ENABLE will read back immediately and the Synchronization Busy bit in the Status regis-
ter (STATUS.SYNCBUSY) will be set. STATUS.SYNCBUSY is cleared when the operation is complete.

This bit is not enable-protected.

z

Bit 0 – SWRST: Software Reset
0: There is no reset operation ongoing.

1: The reset operation is ongoing.

Writing a zero to this bit has no effect. 

Writing a one to this bit resets all registers in the SERCOM, except DBGCTRL, to their initial state, and the SER-
COM will be disabled. 

Writing a one to CTRLA.SWRST will always take precedence, meaning that all other writes in the same write-oper-
ation will be discarded. 

Due to synchronization, there is a delay from writing CTRLA.SWRST until the reset is complete. CTRLA.SWRST 
and STATUS.SYNCBUSY will both be cleared when the reset is complete.

This bit is not enable-protected.