Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
349
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
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Bit 30 – DORD: Data Order
This bit indicates the data order when a character is shifted out from the Data register.
This bit indicates the data order when a character is shifted out from the Data register.
0: MSB is transmitted first.
1: LSB is transmitted first.
This bit is not synchronized.
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Bit 29 – CPOL: Clock Polarity
This bit indicates the relationship between data output change and data input sampling in synchronous mode.
This bit indicates the relationship between data output change and data input sampling in synchronous mode.
This bit is not synchronized.
Table 24-3. Clock Polarity
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Bit 28 – CMODE: Communication Mode
This bit indicates asynchronous or synchronous communication.
This bit indicates asynchronous or synchronous communication.
0: Asynchronous communication.
1: Synchronous communication.
This bit is not synchronized.
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Bits 27:24 – FORM[3:0]: Frame Format
These bits define the frame format.
These bits define the frame format.
These bits are not synchronized.
Table 24-4. Frame Format
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Bits 23:22 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
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Bits 21:20 – RXPO[1:0]: Receive Data Pinout
These bits define the receive data (RxD) pin configuration.
These bits define the receive data (RxD) pin configuration.
These bits are not synchronized.
CPOL
TxD Change
RxD Sample
0x0
Rising XCK edge
Falling XCK edge
0x1
Falling XCK edge
Rising XCK edge
FORM[3:0]
Description
0x0
USART frame
0x1
USART frame with parity
0x2-0xF
Reserved