Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO Data Sheet
Product codes
ATSAMD20-XPRO
350
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
z
Bits 19:17 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 16 – TXPO: Transmit Data Pinout
This bit defines the transmit data (TxD) and XCK pin configurations.
This bit defines the transmit data (TxD) and XCK pin configurations.
This bit is not synchronized.
Table 24-6. Transmit Data Pinout
z
Bits 15:9 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bit 8 – IBON: Immediate Buffer Overflow Notification
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.
This bit controls when the buffer overflow status bit (STATUS.BUFOVF) is asserted when a buffer overflow occurs.
0: STATUS.BUFOVF is asserted when it occurs in the data stream.
1: STATUS.BUFOVF is asserted immediately upon buffer overflow.
z
Bit 7 – RUNSTDBY: Run In Standby
This bit defines the functionality in standby sleep mode.
This bit defines the functionality in standby sleep mode.
This bit is not synchronized.
Table 24-7. Run In Standby
z
Bits 6:5 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
These bits are unused and reserved for future use. For compatibility with future devices, always write these bits to
zero when this register is written. These bits will always return zero when read.
z
Bits 4:2 – MODE: Operating Mode
Table 24-5. Receive Data Pinout
RXPO[1:0]
Name
Description
0x0
PAD[0]
SERCOM PAD[0] is used for data reception
0x1
PAD[1]
SERCOM PAD[1] is used for data reception
0x2
PAD[2]
SERCOM PAD[2] is used for data reception
0x3
PAD[3]
SERCOM PAD[3] is used for data reception
TXPO
TxD Pin Location
XCK Pin Location (When Applicable)
0x0
PAD[0]
PAD[1]
0x1
PAD[2]
PAD[3]
RUNSTDBY
External Clock
Internal Clock
0x0
External clock is disconnected when
ongoing transfer is finished. All
reception is dropped.
ongoing transfer is finished. All
reception is dropped.
Generic clock is disabled when ongoing transfer is
finished. The device can wake up on Receive Start or
Transfer Complete interrupt.
finished. The device can wake up on Receive Start or
Transfer Complete interrupt.
0x1
Wake on Receive Start or Receive
Complete interrupt.
Complete interrupt.
Generic clock is enabled in all sleep modes. Any
interrupt can wake up the device.
interrupt can wake up the device.