Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

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The AFEC supports 10-bit or 12-bit native resolutions. The 10-bit selection is performed by writing one to the RES
field in the AFEC Extended Mode Register. By default, after a reset, the resolution is the highest and the DATA
field in the data registers is fully used. By writing one to the RES field, the AFEC switches to the lowest resolution
and the conversion results can be read in the lowest significant bits of the data register. The highest bits of the
DATA field of the AFEC_CDR and the highest bits of the LDATA field in the AFEC_LCDR read 0. Writing two,
three or more to the RES field in the AFEC Extended Mode Register (AFEC_EMR) automatically enables the
Enhanced Resolution Mode (see 

 for details).

Moreover, when a PDC channel is connected to the AFEC, resolutions less than 16-bit sets the transfer request
size to 16 bits.

The Enhanced Resolution Mode is automatically enabled when 13-bit,14-bit, 15-bit and 16-bit mode are selected
in the AFEC_EMR. In this mode the AFE Controller will trade conversion performance for accuracy by averaging
multiple samples.

To be able to increase the accuracy by averaging multiple samples it is important that some noise is present in the
input signal. The noise level should be between one and two LSB peak-to-peak to get good averaging
performance.

The performance cost of enabling 13-bit mode is four AFEC samples, which reduces the effective AFEC
performance by the factor 4. This factor equals 16 if the 14-bit mode is selected, 64 if the 15-bit mode is selected,
and 256 if the 16-bit mode is selected. For 14-bit mode this factor is 16. For 14-bit mode the effective sample rate
is maximum AFEC sample rate divided by 16.

When a conversion is completed, the resulting 12-bit digital value is stored in an internal register (1 register for
each channel) that can be read by means of the Channel Data Register (AFEC_CDR) and in the AFEC Last
Converted Data Register (AFEC_LCDR). By setting the TAG option in the AFEC_EMR, the AFEC_LCDR presents
the channel number associated with the last converted data in the CHNB field.

The channel EOC bit in the Status Register (AFEC_ISR) is set and the DRDY bit is set. In the case of a connected
PDC channel, DRDY rising triggers a data transfer request. In any case, either EOC and DRDY can trigger an
interrupt.

Reading the AFEC_CDR clears the EOC bit which index corresponds to the value prior programmed in CSEL field
of the AFEC_CSELR. Reading AFEC_LCDR clears the DRDY bit and EOC bit corresponding to the last converted
channel.