Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

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The Bus Matrix (MATRIX) implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel
access paths between multiple AHB masters and slaves in a system, thus increasing the overall bandwidth. The
Bus Matrix interconnects up to 7 AHB masters to

 

up to 6 AHB slaves. The normal latency to connect a master to a

slave is one cycle except for the default master of the accessed slave which is connected directly (zero cycle
latency). The Bus Matrix user interface is compliant with ARM Advanced Peripheral Bus.

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Configurable Number of Masters (up to 7)



Configurable Number of Slaves (up to 6)



One Decoder for Each Master

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Several Possible Boot Memories for Each Master before Remap



One Remap Function for Each Master



Support for Long Bursts of 32, 64, 128 and up to the 256-beat Word Burst AHB Limit



Enhanced Programmable Mixed Arbitration for Each Slave

̶

Round-Robin

̶

Fixed Priority



Programmable Default Master for Each Slave

̶

No Default Master

̶

Last Accessed Default Master

̶

Fixed Default Master



Deterministic Maximum Access Latency for Masters



Zero or One Cycle Arbitration Latency for the First Access of a Burst



Bus Lock Forwarding to Slaves

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Master Number Forwarding to Slaves

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One Special Function Register for Each Slave (not dedicated)



Write Protection of User Interface Registers

The Bus Matrix manages 7 masters, which means that each master can perform an access concurrently with
others, to an available slave. 

Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing,
all the masters have the same decodings.

The Bus Matrix manages 6 slaves. Each slave has its own arbiter, allowing a different arbitration per slave. 

Slave 0

Internal SRAM

Slave 1

Internal ROM

Slave 2

Internal Flash