Atmel Evaluation Kit for the SAM4E Series of Flash Microcontrollers ATSAM4E-EK ATSAM4E-EK Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

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The Bus Matrix provides one decoder for every AHB master interface. The decoder offers each AHB master
several memory mappings. Each memory area may be assigned to several slaves. Booting at the same address
while using different AHB slaves (i.e. external RAM, internal ROM or internal Flash, etc.) becomes possible.

The Bus Matrix user interface provides the Master Remap Control Register (MATRIX_MRCR), that performs
remap action for every master independently.

The Bus Matrix user interface provides Master Remap Control Register (MATRIX_MRCR) that performs remap
action for every master independently.

The Bus Matrix provides some speculative bus granting techniques in order to anticipate access requests from
masters. This mechanism reduces latency at first access of a burst, or for a single transfer, as long as the slave is
free from any other master access. It does not provide any benefit if the slave is continuously accessed by more
than one master, since arbitration is pipelined and has no negative effect on the slave bandwidth or access
latency.

This bus granting mechanism sets a different default master for every slave.

At the end of the current access, if no other request is pending, the slave remains connected to its associated
default master. A slave can be associated with three kinds of default masters:



No default master



Last access master



Fixed default master

To change from one type of default master to another, the Bus Matrix user interface provides the Slave
Configuration Registers, one for every slave, that set a default master for each slave. The Slave Configuration
Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The 2-bit DEFMSTR_TYPE field selects
the default master type (no default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR
field selects a fixed default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to

.

After the end of the current access, if no other request is pending, the slave is disconnected from all masters.

This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without
default master may be used for masters that perform significant bursts or several transfers with no Idle in between,
or if the slave bus bandwidth is widely used by one or more masters.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput whatever the number of requesting masters.