Taskit ARM9 CPU-module with Linux Stamp9261-series Stamp9261 (64F/64R) 542310 Data Sheet
Product codes
542310
4.8. Real-time Timer (RTT)
The Real-time Timer is a 32-bit counter combined with a 16-bit prescaler running at Slow Clock
(SLCK = 32768 Hz). As the RTT keeps running if only the backup supply voltage is availbale, it is used
as a Real-time clock on the Stamp9261.
(SLCK = 32768 Hz). As the RTT keeps running if only the backup supply voltage is availbale, it is used
as a Real-time clock on the Stamp9261.
The RTT can generate an interrupt every time the prescaler rolls over. Usually the RTT is configured
to generate an interrupt every second, so the prescaler will be programmed with the value 7FFFh.
to generate an interrupt every second, so the prescaler will be programmed with the value 7FFFh.
The RTT can also generate an alarm if a preprogrammed 32-bit value is reached by the counter.
4.9. Timer Counter (TC)
The TC consists of three independent 16-bit Timer/Counter units. They may be cascaded to form a 32-
bit or 48-bit timer/counter. On the Stamp9261, the external signals are not available as they are
multiplexed on the Processor with the upper 16 bits of the data bus. The timers can therefore only run
on the internal clock sources:
bit or 48-bit timer/counter. On the Stamp9261, the external signals are not available as they are
multiplexed on the Processor with the upper 16 bits of the data bus. The timers can therefore only run
on the internal clock sources:
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MCK/2, MCK/8, MCK/32, MCK/128, SLCK,
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or the output of another timer channel.
4.10. Periodic Interval Timer (PIT)
The PIT consists of a 20-bit counter running on MCK / 16. This counter can be preloaded with any
value between 1 and 2
value between 1 and 2
20
. The counter increments until the preloaded value is reached. At this stage it
rolls over and generates an interrupt. An additional 12-bit counter counts the interrupts of the 20 bit
counter.
counter.
The PIT is intended for use as the operating system’s scheduler interrupt.
4.11. Watchdog Timer
The watchdog timer is a 12-bit timer running at 256 Hz (Slow Clock / 128) The maximum watchdog
timeout period is therefore equal to 16 seconds. If enabled, the watchdog timer asserts a hardware
reset at the end of the timeout period. The application program must always reset the watchdog timer
before the timeout is reached. If an application program has crashed for some reason, the watchdog
timer will reset the system, thereby reproducing a well defined state once again.
timeout period is therefore equal to 16 seconds. If enabled, the watchdog timer asserts a hardware
reset at the end of the timeout period. The application program must always reset the watchdog timer
before the timeout is reached. If an application program has crashed for some reason, the watchdog
timer will reset the system, thereby reproducing a well defined state once again.
The Watchdog Mode Register can be written only once. After a Processor Reset, the watchdog is
already activated and running with the maximum timeout period. Once the watchdog has been
reconfigured or deactivated by writing to the Watchdog Mode Register, only a Processor Reset can
change its mode once again.
already activated and running with the maximum timeout period. Once the watchdog has been
reconfigured or deactivated by writing to the Watchdog Mode Register, only a Processor Reset can
change its mode once again.
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