Taskit ARM9 CPU-module with Linux Stamp9261-series Stamp9261 (64F/64R) 542310 Data Sheet
Product codes
542310
4.12. Bus Matrix
The SAM9261 Processor's Bus Matrix consists of 5 masters and 5 slaves:
The Bus Masters are:
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ARM926EJS Core Instruction Fetch,
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ARM926EJS Core Data I/O,
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USB Host DMA,
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LCDC-DMA,
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Peripheral DMA Controller (PDC).
Bus Slaves are:
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internal ROM,
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internal SRAM,
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EBI,
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internal peripherals,
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LCDC and USB Host port.
EBI connects to external devices. In the case of the Stamp9261 these consist in the SDRAM, the flash
memory and the Ethernet Controller. The LCDC and the USB Host ports share a common slave bus
connection.
memory and the Ethernet Controller. The LCDC and the USB Host ports share a common slave bus
connection.
The Bus Matrix provides independent paths for each Master/Slave connection. For example, the
LCDC-DMA can fetch video data from its video RAM (which we assume is allocated within the
SDRAM) at the same time as the USART DMA (a PDC channel) stores data within the internal SRAM.
LCDC-DMA can fetch video data from its video RAM (which we assume is allocated within the
SDRAM) at the same time as the USART DMA (a PDC channel) stores data within the internal SRAM.
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