STMicroelectronics FlexSPIN: SPI configurable stepper and DC multi motor driver evaluation board EVAL6460 EVAL6460 Data Sheet
Product codes
EVAL6460
L6460
GPIO pins
Doc ID 17713 Rev 1
109/139
22.6 GPIO[5]
).
Table 46.
GPIO[5] truth table
Master
(1)
1.
Master bit is at logic level “1” when
L6460
is used as a master device (see
)
AUX1
system
and
Vloop1
external
(2)
2.
This bit is at logic level “1” if AUX1 regulator is a system regulator but its power stage is externally realized
(and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic
level “1”, while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level “0” in
CoreConfigReg register.
(and therefore the regulation loop is not used to drive bridge 3). In this case Vloop1IsSys bit will be at logic
level “1”, while Vloop1OnMtr3SideA and Vloop1OnMtr3SideB bits will be at logic level “0” in
CoreConfigReg register.
GPIO[5] SPI BITS
Function
Note
GpioOut
enable[5]
Mode[2]
Mode[1]
Mode[0]
1
X
X
X
X
X
Slave control
0
1
X
X
X
X
Reg Loop1 OUT
(3)
3.
In all configurations in which GPIO[5] is enabled as output:
a) the GPIO[5] pin can be always used as an analog input to the ADC system (ADC function) by writing its
address in the A2DChannelX[4:0] in the A2DConfigX register and starting a conversion;
b) the GPIO[5] pin can be always used as a digital input so its value can be always read through SPI
interface (SPI_IN function);
c)
the GPIO[5] pin is a rail to rail, back to back output supplied by V
3v3
.
0
0
0
X
X
X
HiZ (SPI_IN)
0
0
1
0
0
0
SPI OUT
0
0
1
0
0
1
Comp1OUT
0
0
1
0
1
0
Reg Loop1 OUT
0
0
1
0
1
1
AuxPwm3
0
0
1
1
0
0
SPI OUT inverted
0
0
1
1
0
1
Comp1OUT inverted
0
0
1
1
1
0
Reg Loop1 OUT
inverted
0
0
1
1
1
1
AuxPwm3 inverted