STMicroelectronics FlexSPIN: SPI configurable stepper and DC multi motor driver evaluation board EVAL6460 EVAL6460 Data Sheet
Product codes
EVAL6460
Supervisory system
L6460
32/139
Doc ID 17713 Rev 1
5 Supervisory
system
The supervisory circuitry monitors the state of several functions inside L6460 and resets the
device (and other ICs if connected to nRESET pin) when the monitored functions are
outside their normal range. Supervisory circuitry can be divided into three main blocks:
device (and other ICs if connected to nRESET pin) when the monitored functions are
outside their normal range. Supervisory circuitry can be divided into three main blocks:
–
Power on reset (POR) generation circuitry.
–
nRESET (nRST_int) generation circuitry.
–
Thermal shut down (TSD) generation circuitry.
POR circuitry monitors the voltages that L6460 needs to guarantee its own functionality;
nRESET circuitry controls if L6460’s main voltages are inside the normal range; TSD is the
thermal shut down of the chip in case of overheating.
nRESET circuitry controls if L6460’s main voltages are inside the normal range; TSD is the
thermal shut down of the chip in case of overheating.
5.1
Power on reset (POR) circuit
Power on reset circuit monitors V
Supply
, and V
3V3
voltages. The purpose of this circuit is to
set the device is in a stable and controlled status until the minimum supply voltages that
guarantee the device functionality are reached. The output signal of this circuit (in the
following indicated as “POR”) becomes active when V
guarantee the device functionality are reached. The output signal of this circuit (in the
following indicated as “POR”) becomes active when V
Supply
or V
3V3
go under their falling
threshold.
When POR output signal is active, all functions and all flags inside L6460 are set in their
reset state; once POR signal comes back from off state (meaning monitored voltages are
above their rising threshold), the power up sequence is re-initialized.
reset state; once POR signal comes back from off state (meaning monitored voltages are
above their rising threshold), the power up sequence is re-initialized.
5.2
nRESET generation circuit
The nRESET circuit monitors V
Supply
, V
SupplyInt
, V
Pump
, V
GPIO_SPI
and all system regulators
(V
System
) voltages. The purpose of this circuit is to prevent the device functionality until the
monitored voltages reach their operative value (please note that V
3v3
is monitored by POR,
so it must be above its minimum value, otherwise nRESET circuit is not active).
This circuit generates an internal reset signal (in the following indicated as “nRST_int”) that
will also be signaled to external circuits by pulling low the nRESET pin.
will also be signaled to external circuits by pulling low the nRESET pin.
The signal nRST_int becomes active in the following cases:
1.
When one of the following voltages is lower than its own under voltage threshold:
–
V
Supply
and V
SupplyInt
.
–
V
Pump
.
–
V
System
(all switching or linear system regulators voltages).
–
V
GPIO_SPI
.
2.
When watchdog timer counter (see
) elapse the watchdog timeout time (only
if watchdog function is enabled).
3.
When L6460 is in “Low Power mode”.
4.
When EnExtSoftRst bit in SoftResReg register is at logic level = “1” and a “SoftRes”
command is applied (see SoftResReg register description in
command is applied (see SoftResReg register description in
).
When an nRST_int event is caused by above cases, the nRESET pin will stay low for a
“stretch” time that starts from the moment that nRST_int signal returns in the operative
“stretch” time that starts from the moment that nRST_int signal returns in the operative