Intel III Xeon 667 MHz 80526KZ667256 Data Sheet

16

A Debug Port is described in Chapter 8. The Debug Port must be placed at the start and end of the TAP chain with TDI to
the first component coming from the Debug Port and TDO from the last component going to the Debug Port. In an MP
system, be cautious when including an empty SC330 connector in the scan chain. All connectors in the scan chain must
have a processor or termination card installed to complete the chain between TDI and TDO or the system must support a
method to bypass the empty connectors. SC330 terminator substrates should tie TDI directly to TDO. (See Chapter 8 for
more details.)

Functional operation at the absolute maximum and minimum is not implied nor guaranteed. The processor should not
receive a clock while subjected to these conditions. Functional operating conditions are given in the AC and DC tables.
Extended exposure to the maximum ratings may affect device reliability. Furthermore, although the processor contains
protective circuitry to resist damage from static electric discharge, one should always take precautions to avoid high static
voltages or electric fields.

T

STORAGE

Processor storage temperature

–40

85

°C

VCC_CORE

Supply voltage with respect to
V

SS 

seen at the input of the

OCVR

–0.5

Operating

voltage + 1.0

V

1,2

V

SMBus

Any processor SM supply
voltage with respect to V

SS

-0.3

Operating

voltage + 1.0

V

V

CCTAP

Any processor TAP supply
voltage with respect to V

SS

-0.3

3.3

V

1

V

inGTL

AGTL+ buffer DC input voltage
with respect to V

SS

–0.3

+ 1.65

V

V

inCMOS

CMOS & APIC buffer DC input
voltage with respect to V

SS

–0.3

3.3

V

V

inSMBus

SMBus buffer DC input voltage
with respect to V

SS

-0.1

7.0

V

I

PWR_EN

Max PWR_EN[1:0] pin current

100

mA

1. 

Operating voltage is the voltage to which the component is designed to operate. See  Table 5.

2. 

VCC_CORE  

in the case of Pentium® III Xeon™ processor at 600 MHz+ is the voltage input seen at the input of the OCVR device

which may be 2.8V for one product version or 5V (or 12V) for another product version.

3. 

Please contact Intel for storage requirements in excess of one year.

The voltage and current specifications provided Table 6 are defined at the processor edge fingers. The processor signal
DC specifications in Tables 7, 8 and 9 are defined at the Pentium III Xeon processor at 600 MHz+ core. Each signal trace
between the processor edge finger and the processor core carries a small amount of current and has a finite resistance.
The current produces a voltage drop between the processor edge finger and the core. Simulations should therefore be run
versus these specifications to the processor core.

See Chapter 1 for the processor edge finger signal definitions and Table 3  for the signal grouping.

Most of the signals on the Pentium III Xeon processor at 600 MHz+ system bus are in the AGTL+ signal group. These
signals are specified to be terminated to VTT. The DC specifications for these signals are listed in Table 7.

To ease connection with other devices, the Clock, CMOS, APIC, SMBus and TAP signals are designed to interface at
non-AGTL+ levels. Pentium III Xeon processor at 600 MHz+ contain a voltage clamp device on the cartridge substrate
between the core and edge fingers.  This device “clamps” the 2.5V level CMOS, TAP, and APIC signals to 1.5V levels,
which helps reduce overshoot levels at the processor core.  All CMOS, TAP, Clock, and APIC signals interface with the