Intel III Xeon 667 MHz 80526KZ667256 Data Sheet
Product codes
80526KZ667256
PENTIUM® III XEON™ PROCESSOR AT 600 MHz to 1 GHz with 256KB L2 Cache
ELECTRICAL SPECIFICATIONS
15
Table 3. Processor pin Groups
Group Name
Signals
AGTL+ Input
BPRI#, BR[3:1]#1, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#
AGTL+ Output
PRDY#
AGTL+ I/O
A[35:03]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#, BNR#, BP[3:2]#, BPM[1:0]#,
BR0#1, D[63:00]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#,
REQ[4:0]#, RP#
BR0#1, D[63:00]#, DBSY#, DEP[7:0]#, DRDY#, HIT#, HITM#, LOCK#,
REQ[4:0]#, RP#
CMOS Input
A20M#, FLUSH#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, PREQ#, PWRGD2,
SMI#, SLP#2, STPCLK#
SMI#, SLP#2, STPCLK#
CMOS Output
FERR#, IERR#, THERMTRIP#2
System Bus Clock
BCLK
APIC Clock
PICCLK
APIC I/O3
PICD[1:0]
TAP Input
TCK, TDI, TMS, TRST#
TAP Output3
TDO
SMBus Interface
SMBDAT, SMBCLK, SMBALERT#, WP
Power/Other4
VCC_CORE, VCC_TAP, VCC_SMB, VTT, VSS, RESERVED_XXX, SA[2:1],
SELFSB[0:1], OCVR_EN, OCVR_OK, VIN_SENSE, CORE_AN_VSENSE,
HV_EN#
SELFSB[0:1], OCVR_EN, OCVR_OK, VIN_SENSE, CORE_AN_VSENSE,
HV_EN#
NOTES:
1.
The BR0# pin is the only BREQ# signal that is bi-directional. The internal BREQ# signals are mapped onto BR# pins based on a
processor’s agent ID. See Chapter 10 for more information.
processor’s agent ID. See Chapter 10 for more information.
2.
For information on these signals, see Chapter 10.
3.
These signals are specified for 2.5V operation.
4. VTT is used for the AGTL+ termination.
VSS is system ground.
VCC_TAP is the TAP supply.
VCC_SMB is the SM bus supply.
Reserved pins must be left unconnected. Do not connect to each other.
VCC_TAP is the TAP supply.
VCC_SMB is the SM bus supply.
Reserved pins must be left unconnected. Do not connect to each other.
3.7.2 ASYNCHRONOUS VS. SYNCHRONOUS FOR SYSTEM BUS SIGNALS
All AGTL+ signals are synchronous to BCLK. All of the CMOS, Clock, APIC, and TAP signals can be applied
asynchronously to BCLK.
asynchronously to BCLK.
All APIC signals are synchronous to PICCLK. All TAP signals are synchronous to TCK. All SMBus signals are
synchronous to SMBCLK. TCK and SMBCLK can be asynchronous to all other clocks.
synchronous to SMBCLK. TCK and SMBCLK can be asynchronous to all other clocks.
3.8 Access Port (TAP) Connection
Depending on the voltage levels supported by other components in the Test Access Port (TAP) logic, it is recommended
that the Pentium® III Xeon™ processor at 600 MHz+ be first in the TAP chain and followed by any other components
within the system. A voltage translation buffer should be used to drive the next device in the chain unless a component is
used that is capable of accepting a 2.5V input. Similar considerations must be made for TCK, TMS, and TRST#. Multiple
copies of each TAP signal may be required if multiple voltage levels are needed within a system.
that the Pentium® III Xeon™ processor at 600 MHz+ be first in the TAP chain and followed by any other components
within the system. A voltage translation buffer should be used to drive the next device in the chain unless a component is
used that is capable of accepting a 2.5V input. Similar considerations must be made for TCK, TMS, and TRST#. Multiple
copies of each TAP signal may be required if multiple voltage levels are needed within a system.
NOTE
TDI is pulled up to VCCTAP with ~150 ohms on the Pentium III Xeon processor at 600 MHz+ cartridge. An
open drain signal driving this pin must be able to deliver sufficient current to drive the signal low. Also, no
resistor should exist in the system design on this pin, as it would be in parallel with this resistor.
resistor should exist in the system design on this pin, as it would be in parallel with this resistor.