Intel III Xeon 667 MHz 80526KZ667256 Data Sheet

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Unless otherwise specified, All RESERVED_XXX pins must remain unconnected. Note that pins that are newly marked as
RESERVED in this document may be tied to a power rail in existing baseboards. Connection of RESERVED_XXX pins to
VCC_CORE, VSS or  VTT , to each other or to any other signal can result in component malfunction or incompatibility
with future members of the Pentium® III Xeon™ processor at 600 MHz+ family. See Chapter 7 for a pin listing of the
processor edge connector for the location of each reserved pin.

The TEST_2.5_A62 pin must be connected to 2.5 Volts via a pull-up resistor between 1K  and 10K ohms.

For the 5/12V Pentium III Xeon processor only, it is recommended that pins that were previously specified as
TEST_VCC_CORE_XX (now specified TEST_2.5_XX), be connected to the VCC_2.5 supply through separate 10K ohm
resistors on the baseboard. However, there will be no damage to cartridges if existing platforms provide 2.8 Volts to the
pull-up resistors.  All TEST_VTT pins must be connected to the V

TT

 supply through individual 150 ohm resistors. All

TEST_VSS pins must be connected individually to the VSS supply through individual 1K-ohm resistors.

PICCLK must always be driven with a valid clock input, and the PICD[1:0] lines must be pulled-up to 2.5V even when the
APIC will not be used. A separate pull-up resistor to 2.5V (keep trace short) is required for each PICD line.

For reliable operation, always connect unused inputs to an appropriate signal level. Unused AGTL+ inputs should be left
as no connects; AGTL+ termination on the processor provides a high level. Unused active low CMOS inputs should be
connected to 2.5V  with a ~10K ohm resistor. Unused active high CMOS inputs should be connected to ground (VSS).
Unused outputs may be left unconnected. A resistor must be used when tying bi-directional signals to power or ground.
When tying any signal to power or ground, a resistor will also allow for system testability. For correct operation when using
a logic analyzer interface, refer to Chapter 8 for design considerations.

In order to simplify the following discussion, the system bus signals have been combined into groups by buffer type. All
system bus outputs should be treated as open drain and require a high-level source provided externally by the termination
or pull-up resistor.

AGTL+ input signals have differential input buffers, which use 2/3 V TT as a reference level. AGTL+ output signals require
termination to 1.5V. In this document, the term "AGTL+ Input" refers to the AGTL+ input group as well as the AGTL+ I/O
group when receiving. Similarly, "AGTL+ Output" refers to the AGTL+ output group as well as the AGTL+ I/O group when
driving. The AGTL+ buffers employ active negation for one clock cycle after assertion to improve rise times.

The CMOS, Clock, APIC, and TAP inputs can each be driven from ground to 2.5V. The CMOS, APIC, and TAP outputs
are open drain and should be pulled high to 2.5V. This ensures not only correct operation for Pentium III Xeon processor
at 600 MHz+, but compatibility with future Pentium III Xeon processors at 600 MHz+. Timings are specified into the load
resistance as defined in the AC timing tables. See Chapter 8 for design considerations for debug equipment.

 The SMBus signals should be driven using standard 3.3V CMOS logic levels.