Intel T5470 LF80537GG0252M Data Sheet

Datasheet

21

The processor incorporates FSB low power enhancements:

• Dynamic FSB Power Down
• BPRI# control for address and control input buffers
• Dynamic Bus Parking
• Dynamic On-Die Termination disabling
• Low  V

CCP

 (I/O termination voltage)

• Dynamic FSB frequency switching

The processor incorporates the DPWR# signal that controls the data bus input buffers 

on the processor. The DPWR# signal disables the buffers when not used and activates 

them only when data bus activity occurs, resulting in significant power savings with no 

performance impact. BPRI# control also allows the processor address and control input 

buffers to be turned off when the BPRI# signal is inactive. Dynamic Bus Parking allows 

a reciprocal power reduction in GMCH address and control input buffers when the 

processor deasserts its BR0# pin. The On-Die Termination on the processor FSB buffers 

is disabled when the signals are driven low, resulting in additional power savings. The 

low I/O termination voltage is on a dedicated voltage plane independent of the core 

voltage, enabling low I/O switching power at all times. 

Dynamic FSB frequency switching effectively reduces the internal bus clock frequency 

in half to further decrease the minimum processor operating frequency from the 

Enhanced Intel SpeedStep Technology performance states and achieve the Super Low 

Frequency Mode (Super LFM). This feature is supported at FSB frequencies of 

1066 MHz, 800 MHz and 667 MHz and does not entail a change in the external bus 

signal (BCLK) frequency. Instead, both the processor and GMCH internally lower their 

BCLK reference frequency to 50% of the externally visible frequency. Both the 

processor and GMCH maintain a virtual BCLK signal (VBCLK) that is aligned to the 

external BCLK but at half the frequency. After a downward shift, it would appear 

externally as if the bus is running with a 133-MHz base clock in all aspects, except that 

the actual external BCLK remains at 266 MHz. See 

 for details. The transition 

into Super LFM, a “down-shift,” is done following a handshake between the processor 

and GMCH. A similar handshake is used to indicate an “up-shift,” a change back to 

normal operating mode. Please ensure this feature is enabled and supported in the 

BIOS.