Intel T5470 LF80537GG0252M Data Sheet

Datasheet

23

When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be 

active under certain internal conditions. In such a scenario the processor may draw a 

Instantaneous current (I

CC_CORE_INST)

 for a short duration of t

INST

; however, the 

average I

CC

 current will be lesser than or equal to I

CCDES

 current specification. Please 

refer to the Processor DC Specifications section for more details.

The processor implements the VID-x feature for improved control of core voltage levels 

when the processor enters a reduced power consumption state. VID-x applies only 

when the processor is in the Intel Dynamic Acceleration Technology performance state 

and one or more cores are in low-power state (i.e., CC3/CC4/CC6). VID-x provides the 

ability for the processor to request core voltage level reductions greater than one VID 

tick. The amount of VID tick reduction is fixed and only occurs while the processor is in 

Intel Dynamic Acceleration Technology mode. This improved voltage regulator 

efficiency during periods of reduced power consumption allows for leakage current 

reduction which results in platform power savings and extended battery life. 

When in Intel Dynamic Acceleration Technology mode, it is possible for both cores to be 

active under certain internal conditions. In such a scenario the processor may draw a 

Instantaneous current (I

CC_CORE_INST)

 for a short duration of t

INST

; however, the 

average I

CC

 current will be lesser than or equal to I

CCDES

 current specification. Please 

refer to the Processor DC Specifications section for more details.

The processor incorporates the PSI# signal that is asserted when the processor is in a 

reduced power consumption state. PSI# can be used to improve intermediate and light 

load efficiency of the voltage regulator, resulting in platform power savings and 

extended battery life. The algorithm that the processor uses for determining when to 

assert PSI# is different from the algorithm used in previous mobile processors. PSI-2 

functionality is expanded further to support three processor states:

• Both cores are in idle state 
• Only one core active state
• Both cores are in active state

PSI-2 functionality improves overall voltage regulator efficiency over a wide power 

range based on the C-state and P-state of the two cores. The combined C-state and P-

state of both cores are used to dynamically predict processor power. 

The real-time power prediction is compared against a set of predefined and configured 

values of CHH and CHL. CHH is indicative of the active C-state of both the cores and 

CHL is indicative that only one core is in active C-state and the other core is in low 

power core state. PSI-2# output is asserted upon crossing these thresholds indicating 

that the processor requires lower power. The voltage regulator will adapt its power 

output accordingly. Additionally the voltage regulator may switch to a single phase and/

or asynchronous mode when the processor is idle and fused leakage limit is less than or 

equal to the BIOS threshold value.

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