Intel T5470 LF80537GG0252M Data Sheet

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Datasheet

NOTES:
1.

All common clock signals will be active for two BCLKs instead of one (e.g., ADS#, HIT#).

2.

The double-pumped signal strobes will have only one transition per BCLK when active, 
instead of two.

3.

The quad-pumped signal strobes will have only two transitions per BCLK when active, 
instead of four.

4.

Same setup and hold times apply, but relative to every second rising BCLK.

5.

Following a RESET#, the bus will be in the legacy full-frequency mode.

6.

There will not be a down-shift right after RESET# deassertion. 

7.

There is no backing out of a transition into or out of half-frequency mode. Once the 
sequence starts it must be completed. 

The processor supports Intel Dynamic Acceleration Technology mode. The Intel 

Dynamic Acceleration Technology feature allows one core of the processor to operate at 

a higher frequency point when the other core is inactive and the operating system 

requests increased performance. This higher frequency is called the opportunistic 

frequency and the maximum rated operating frequency is the ensured frequency. 

The processor includes a hysteresis mechanism that improves overall Intel Dynamic 

Acceleration Technology performance by decreasing unnecessary transitions of the 

cores in and out of Intel Dynamic Acceleration Technology mode. Normally, the 

processor would exit Intel Dynamic Acceleration Technology as soon as two cores are 

active. This can become an issue if the idle core is frequently awakened for a short 

periods (i.e., high timer tick rates). The hysteresis mechanism allows two cores to be 

active for a limited time before it transitions out of Intel Dynamic Acceleration 

Technology mode.

Intel Dynamic Acceleration Technology mode enabling requires:

• Exposure, via BIOS, of the opportunistic frequency as the highest ACPI P state
• Enhanced Multi-Threaded Thermal Management (EMTTM)
• Intel Dynamic Acceleration Technology mode and EMTTM MSR configuration via 

BIOS.