Intel III Xeon 900 MHz 80526KY9002M Data Sheet

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The Pentium III Xeon processor at 600MHz+ signals uses a variation of the Pentium Pro processor GTL+ signaling
technology. The Pentium III Xeon processor at  600 MHz+ differs from the Pentium II processor and Pentium Pro
processor in its output buffer implementation. The buffers that drive most of the system bus signals on the Pentium III
Xeon processor at 600 MHz+ are actively driven to V TT for one clock cycle after the low to high transition to improve rise-
times and reduce noise. These signals should still be considered open-drain and require termination to a supply that
provides the high signal level. Because this specification is different from the standard GTL+ specification, it is referred to
as Assisted Gunning Transistor Logic (AGTL+) in this document. AGTL+ logic and GTL+ logic are compatible with each
other and may both be used on the same system bus. For more information on the GTL+ specification, see the Pentium
Pro Family Developer’s Manual Volume I (Order Number 242690).

AGTL+ inputs use differential receivers that require a reference signal (VREF). VREF is used by the receivers to
determine if a signal is a logical 0 or a logical 1. The Pentium III Xeon processor at 600 MHz+ generates its own version of
VREF. VREF must be generated on the baseboard for other devices on the AGTL+ system bus. Termination is used to
pull the bus up to the high voltage level and to control signal integrity on the transmission line. The processor contains on-
cartridge termination resistors that provide termination for the AGTL bus. These specifications assume the equivalent of 5
(FIVE) AGTL+ loads and termination resistors to ensure the proper timings on rising and falling edges. See test conditions
described with each specification.

Like the Pentium III Xeon™ processor, the timing specifications of the Pentium III Xeon processor at  600 MHz+ are
defined to points internal to the processor packaging. Analog signal simulation of the system bus is required when
developing Pentium III Xeon processor at  600 MHz+ based systems to ensure proper operation over all conditions.
Pentium® III Xeon™ Processor Signal Integrity Models are available for simulation.

By implementing an On Cartridge Voltage Regulator (OCVR), the Pentium III Xeon processor at 600 MHz+ eliminates the
need of high precision regulation from the flexible baseboard. Note that the Pentium III Xeon processor at 600 MHz+ does
not require a dedicated L2 supply and that VID logic will assume L2 supply is not required. (Please refer to the VRM 8.3
Guidelines for details).

A 2.8V Pentium® III Xeon™ processor relies on the VID identification pins for the VCC_CORE required voltage level
ONLY and does not require a separate L2 voltage supply. A 5/12V Pentium® III Xeon™ processor does not require a
VRM, and therefore the VID_CORE lines will be “open” on the cartridge (requesting “NO CPU”).

For signal integrity improvement and clean power distribution within the S.E.C. package, the Pentium III Xeon processor
at 600 MHz+ has 65 VCC (power) and 55 V SS (ground) inputs (see section 7.3 for a complete edge finger signal listing).
The 65 VCC pins are further divided to provide the different voltage levels to the components. VCC_CORE inputs for the
processor core account for 35 of the VCC pins, while 8 VTT inputs (1.5V) are used to provide an AGTL+ termination
voltage to the processor. One VCC_SMB pin is provided for use by the SMBus, and one VCC_TAP. The VCC_SMB,
VCC_TAP, and VCC_CORE must remain electrically separated from each other. VCC_SMB must be connected to a 3.3V
power supply (even if the SMBus features are not used) in order for the Pentium III Xeon processor at  600 MHz+ to
function properly. On the baseboard, all VCC_CORE pins must be connected to a voltage plane. Similarly, all VSS pins
must be connected to a system ground plane.