Intel 1.40 GHz RH80532NC017256 Data Sheet

298517-006 Datasheet 

15 

Asserting the STPCLK# signal while in the Auto Halt state will cause the processor to transition to the 
Quick Start state.  Deasserting STPCLK# will cause the processor to return to the Auto Halt state 
without issuing a new Halt bus cycle.  

The SMI# interrupt is recognized in the Auto Halt state. The return from the System Management 
Interrupt (SMI) handler can be to either the Normal state or the Auto Halt state. See the Intel

Architecture Software Developer’s Manual, Volume III: System Programmer’s Guide for more 
information. No Halt bus cycle is issued when returning to the Auto Halt state from the System 
Management Mode (SMM). 

The FLUSH# signal is serviced in the Auto Halt state. After the on-chip and off-chip caches have been 
flushed, the processor will return to the Auto Halt state without issuing a Halt bus cycle. Transitions in 
the A20M# and PREQ# signals are recognized while in the Auto Halt state. 

 
 
 

HS=false

HS=true

STPCLK#

1

BCLK stopped

or DPSLP#

snoop

occurs

BCLK on

and !DPSLP#

(!STPCLK# and !HS)

or RESET#

snoop

serviced

HLT

instruction

1

snoop

serviced

snoop

occurs

STPCLK#

1

!STPCLK#

and HS

halt

break

V0001-022

 

 
 
 
NOTES:   

 

             1. State transition does not occur until the Stop Grant or Auto Halt acknowledge bus cycle completes 
                 Halt break – A20M#, BINIT#, FLUSH#, INIT#, INTR, NMI, PREQ#, RESET#, SMI#, or APIC interrupt 
                 HLT – HLT instruction executed 
                 HS – Processor Halt State 
             2. Restrictions apply to the use of both methods of entering Deep Sleep. See Deep Sleep state description for details. 

The processor is required to be configured for the Quick Start state by strapping the A15# signal low. In 
the Quick Start state the processor is only capable of acting on snoop transactions generated by the 
system bus priority device. Because of its snooping behavior, Quick Start can only be used in a 
uniprocessor (UP) configuration.