Intel 1.40 GHz RH80532NC017256 Data Sheet

16 Datasheet

 

298517-006 

A transition to the Deep Sleep state can be made by stopping the clock input to the processor or asserting 
the DPSLP# signal. A transition back to the Normal state (from the Quick Start state) is made only if the 
STPCLK# signal is deasserted. 

While in this state the processor is limited in its ability to respond to input. It is incapable of latching any 
interrupts, servicing snoop transactions from symmetric bus masters, or responding to FLUSH# or 
BINIT# assertions. While the processor is in the Quick Start state, it will not respond properly to any 
input signal other than STPCLK#, RESET#, or BPRI#. If any other input signal changes, then the 
behavior of the processor will be unpredictable. No serial interrupt messages may begin or be in progress 
while the processor is in the Quick Start state.  

RESET# assertion will cause the processor to immediately initialize itself, but the processor will stay in 
the Quick Start state after initialization until STPCLK# is deasserted. 

The processor will respond to snoop transactions on the system bus while in the Auto Halt or Quick Start 
state. When a snoop transaction is presented on the system bus the processor will enter the HALT/Grant 
Snoop state. The processor will remain in this state until the snoop has been serviced and the system bus 
is quiet. After the snoop has been serviced, the processor will return to its previous state. If the 
HALT/Grant Snoop state is entered from the Quick Start state, then the input signal restrictions of the 
Quick Start state still apply in the HALT/Grant Snoop state, except for those signal transitions that are 
required to perform the snoop. 

The Deep Sleep state is a very low power state that the processor can enter while maintaining its context. 
The Deep Sleep state is entered by stopping the BCLK and BCLK# inputs to the processor or by 
asserting the DPSLP# signal, while it is in the Quick Start state.  Note that either one of the methods can 
be used to enter Deep Sleep but not both at the same time. When BCLK and BCLK# are stopped, they 
must obey the DC levels specified in Table 38 and Table 39. 

The processor will return to the Quick Start state from the Deep Sleep state when the BCLK and BCLK# 
inputs are restarted or the DPSLP# signal is deasserted. Due to the PLL lock latency, there is a delay of 
up to 30 

µsec after the clocks have started before this state transition happens. PICCLK may be removed 

in the Deep Sleep state. PICCLK should be designed to turn on when BCLK and BCLK# turn on or 
DPSLP# is deasserted when transitioning out of the Deep Sleep state.