Intel 1.40 GHz RH80532NC017256 Data Sheet
Product codes
RH80532NC017256
Mobile Intel
®
Celeron
®
Processor (0.13 µ)
Micro-FCBGA and Micro-FCPGA Packages Datasheet
298517-006 Datasheet
17
Table 2. Clock State Characteristics
Clock State
Exit Latency
Snooping?
System Uses
Normal N/A
Yes Normal
program
execution
Auto Halt
10
µsec
Yes
S/W controlled entry idle mode
Quick Start
Through snoop, to
HALT/Grant Snoop state:
immediate
Through STPCLK#, to
Normal state:
HALT/Grant Snoop state:
immediate
Through STPCLK#, to
Normal state:
10 µsec
Yes
H/W controlled entry/exit mobile throttling
HALT/Grant
Snoop
Snoop
A few bus clocks after
snoop completion
snoop completion
Yes
Supports snooping in the low power states
Deep Sleep
30
µsec
No
H/W controlled entry/exit mobile powered-on
suspend support
suspend support
2.2.7
Operating System Implications of Low-power States
The time-stamp counter and the performance monitor counters are not guaranteed to count in the Quick
Start state. The local APIC timer and performance monitor counter interrupts should be disabled before
entering the Deep Sleep state or the resulting behavior will be unpredictable.
Start state. The local APIC timer and performance monitor counter interrupts should be disabled before
entering the Deep Sleep state or the resulting behavior will be unpredictable.
2.3 AGTL
Signals
The Mobile Intel Celeron Processor system bus signals use a variation of the low-voltage swing GTL
signaling technology. The AGTL system bus depends on incident wave switching and uses flight time
for timing calculations of the AGTL signals, as opposed to capacitive derating. Intel recommends analog
signal simulation of the system bus including trace lengths. Contact your field sales representative to
receive the IBIS models for the Mobile Intel Celeron Processor.
signaling technology. The AGTL system bus depends on incident wave switching and uses flight time
for timing calculations of the AGTL signals, as opposed to capacitive derating. Intel recommends analog
signal simulation of the system bus including trace lengths. Contact your field sales representative to
receive the IBIS models for the Mobile Intel Celeron Processor.
The AGTL system bus of the Mobile Intel Celeron Processor is designed to support high-speed data
transfers with multiple loads on a long bus that behaves like a transmission line. However, in mobile
systems the system bus only has two loads (the processor and the chipset) and the bus traces are short. It
is possible to change the layout and termination of the system bus to take advantage of the mobile
environment using the same AGTL I/O buffers. This termination is provided on the processor core
(except for the RESET# signal).
transfers with multiple loads on a long bus that behaves like a transmission line. However, in mobile
systems the system bus only has two loads (the processor and the chipset) and the bus traces are short. It
is possible to change the layout and termination of the system bus to take advantage of the mobile
environment using the same AGTL I/O buffers. This termination is provided on the processor core
(except for the RESET# signal).
2.4
Mobile Intel Celeron Processor CPUID
When the CPUID version information is loaded with EAX=01H, the EAX and EBX registers contain the
values shown in Table 3. After a power-on RESET, the EDX register contains the processor version
information (type, family, model, stepping). Table 4 shows the CPUID Cache and TLB descriptor values
after the L2 cache is initialized. See the Intel Processor Identification and the CPUID Instruction
Application Note AP-485 for further information.
values shown in Table 3. After a power-on RESET, the EDX register contains the processor version
information (type, family, model, stepping). Table 4 shows the CPUID Cache and TLB descriptor values
after the L2 cache is initialized. See the Intel Processor Identification and the CPUID Instruction
Application Note AP-485 for further information.