Intel 807 AV8062701079702 Data Sheet

V

n

Negative-Edge Threshold

Voltage

0.275 * Vcc

ST

0.525 * Vcc

ST

V

—

V

p

Positive-Edge Threshold

Voltage

0.550 * Vcc

ST

0.725 * Vcc

ST

V

—

C

bus

Bus Capacitance per Node

N/A

10

pF

—

C

pad

Pad Capacitance

0.7

1.8

pF

—

Ileak000

leakage current at 0 V

—

0.6

mA

—

Ileak025

leakage current at 0.25*

Vcc

ST

—

0.4

mA

—

Ileak050

leakage current at 0.50*

Vcc

ST

—

0.2

mA

—

Ileak075

leakage current at 0.75*

Vcc

ST

—

0.13

mA

—

Ileak100

leakage current at Vcc

ST

—

0.10

mA

—

Notes: 1. Vcc

ST

 supplies the PECI interface. PECI behavior does not affect Vcc

ST

 minimum / maximum

specifications.

2. The leakage specification applies to powered devices on the PECI bus.
3. The PECI buffer internal pull-up resistance measured at 0.75* Vcc

ST

.

The input buffers in both client and host models must use a Schmitt-triggered input

design for improved noise immunity. Use the following figure as a guide for input

buffer design.

Minimum V

P

Maximum V

P

Minimum V

N

Maximum V

N

PECI High Range

PECI Low Range

Valid Input

Signal Range

Minimum

Hysteresis

V

TTD

PECI Ground

5th Generation Intel

®

 Core

™

 Processor Family, Intel

®

 Core

™

 M Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and

Mobile Intel

®

 Celeron

®

 Processor Family

March 2015

Datasheet – Volume 1 of 2

Order No.: 330834-004v1

95