Intel i3-2328M FF8062701275100 Data Sheet

72

Datasheet, Volume 1

PROCHOT# may be used for thermal protection of voltage regulators (VR). System 
designers can create a circuit to monitor the VR temperature and activate the TCC 
when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) 
and activating the TCC, the VR will cool down as a result of reduced processor power 
consumption. Bi-directional PROCHOT# can allow VR thermal designs to target thermal 
design current (I

CCTDC

) instead of maximum current. Systems should still provide 

proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case 
of system cooling failure. Overall, the system thermal design should allow the power 
delivery circuitry to operate within its temperature specification even while the 
processor is operating at its TDP.

With a properly designed and characterized thermal solution, it is anticipated that 
PROCHOT# will only be asserted for very short periods of time when running the most 
power intensive applications. The processor performance impact due to these brief 
periods of TCC activation is expected to be so minor that it would be immeasurable.

However, an under-designed thermal solution that is not able to prevent excessive 
assertion of PROCHOT# in the anticipated ambient environment may:

• Cause a noticeable performance loss.
• Result in prolonged operation at or above the specified maximum junction 

temperature and affect the long-term reliability of the processor.

• May be incapable of cooling the processor even when the TCC is active continuously 

(in extreme situations).

If the processor enters a low-power package idle state such as C3 or C6/C7 with 
PROCHOT# asserted, PROCHOT# will remain asserted until:

• The processor exits the low-power state
• The processor junction temperature drops below the thermal trip point.

For the package C7 state, PROCHOT# may de-assert for the duration of C7 state 
residency even if the processor enters the idle state operating at the TCC activation 
temperature. The PECI interface is fully operational during all C-states and it is 
expected that the platform continues to manage processor (“package”) core thermals 
even during idle states by regularly polling for thermal data over PECI.

Regardless of enabling the automatic or on-demand modes, in the event of a 
catastrophic cooling failure, the package will automatically shut down when the silicon 
has reached an elevated temperature that risks physical damage to the product. At this 
point the THERMTRIP# signal will go active.

Critical Temperature detection is performed by monitoring the package temperature. 
This feature is intended for graceful shutdown before the THERMTRIP# is activated; 
however, the processor execution is not ensured between critical temperature and 
THERMTRIP#. If the package's Adaptive Thermal Monitor is triggered and the 
temperature remains high, a critical temperature status and sticky bit are latched in the 
PACKAGE_THERM_STATUS MSR 1B1h and also generates a thermal interrupt if