Data Sheet (FF8062701275100)Table of Contents1 Introduction111.1 Processor Feature Details131.1.1 Supported Technologies131.2 Interfaces131.2.1 System Memory Support131.2.2 PCI Express*141.2.3 Direct Media Interface (DMI)151.2.4 Platform Environment Control Interface (PECI)161.2.5 Processor Graphics161.2.6 Embedded DisplayPort* (eDP)171.2.7 Intel® Flexible Display Interface (Intel® FDI)171.3 Power Management Support171.3.1 Processor Core171.3.2 System171.3.3 Memory Controller171.3.4 PCI Express*171.3.5 Direct Media Interface (DMI)171.3.6 Processor Graphics Controller181.4 Thermal Management Support181.5 Package181.6 Terminology181.7 Related Documents202 Interfaces212.1 System Memory Interface212.1.1 System Memory Technology Supported212.1.2 System Memory Timing Support222.1.3 System Memory Organization Modes222.1.3.1 Single-Channel Mode222.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode222.1.4 Rules for Populating Memory Slots232.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)242.1.5.1 Just-in-Time Command Scheduling242.1.5.2 Command Overlap242.1.5.3 Out-of-Order Scheduling242.1.6 Memory Type Range Registers (MTRRs) Enhancement242.1.7 Data Scrambling242.1.8 DRAM Clock Generation242.2 PCI Express* Interface252.2.1 PCI Express* Architecture252.2.1.1 Transaction Layer262.2.1.2 Data Link Layer262.2.1.3 Physical Layer262.2.2 PCI Express* Configuration Mechanism272.2.3 PCI Express Graphics272.2.4 PCI Express* Lanes Connection282.3 Direct Media Interface (DMI)282.3.1 DMI Error Flow282.3.2 Processor / PCH Compatibility Assumptions282.3.3 DMI Link Down292.4 Processor Graphics Controller (GT)292.4.1 3D and Video Engines for Graphics Processing302.4.1.1 3D Engine Execution Units302.4.1.2 3D Pipeline302.4.1.3 Video Engine312.4.1.4 2D Engine312.4.2 Processor Graphics Display322.4.2.1 Display Planes322.4.2.2 Display Pipes332.4.2.3 Display Ports332.4.2.4 Embedded DisplayPort*332.4.3 Intel® Flexible Display Interface (Intel® FDI)332.4.4 Multi-Graphics Controller Multi-Monitor Support342.5 Platform Environment Control Interface (PECI)342.6 Interface Clocking342.6.1 Internal Clocking Requirements343 Technologies353.1 Intel® Virtualization Technology (Intel® VT)353.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Objectives353.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Features363.1.3 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives363.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features373.1.5 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features Not Supported373.2 Intel® Trusted Execution Technology (Intel® TXT)383.3 Intel® Hyper-Threading Technology (Intel® HT Technology)383.4 Intel® Turbo Boost Technology393.4.1 Intel® Turbo Boost Technology Frequency393.4.2 Intel® Turbo Boost Technology Graphics Frequency403.5 Intel® Advanced Vector Extensions (Intel® AVX)403.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)403.6.1 PCLMULQDQ Instruction413.7 Intel® 64 Architecture x2APIC414 Power Management434.1 Advanced Configuration and Power Interface (ACPI) States Supported444.1.1 System States444.1.2 Processor Core / Package Idle States444.1.3 Integrated Memory Controller States444.1.4 PCI Express* Link States454.1.5 Direct Media Interface (DMI) States454.1.6 Processor Graphics Controller States454.1.7 Interface State Combinations454.2 Processor Core Power Management464.2.1 Enhanced Intel® SpeedStep® Technology464.2.2 Low-Power Idle States474.2.3 Requesting Low-Power Idle States484.2.4 Core C-states494.2.4.1 Core C0 State494.2.4.2 Core C1/C1E State494.2.4.3 Core C3 State494.2.4.4 Core C6 State494.2.4.5 Core C7 State494.2.4.6 C-State Auto-Demotion504.2.5 Package C-States504.2.5.1 Package C0514.2.5.2 Package C1/C1E524.2.5.3 Package C3 State524.2.5.4 Package C6 State524.2.5.5 Package C7 State534.2.5.6 Dynamic L3 Cache Sizing534.3 Integrated Memory Controller (IMC) Power Management534.3.1 Disabling Unused System Memory Outputs534.3.2 DRAM Power Management and Initialization544.3.2.1 Initialization Role of CKE554.3.2.2 Conditional Self-Refresh554.3.2.3 Dynamic Power-down Operation564.3.2.4 DRAM I/O Power Management564.4 PCI Express* Power Management564.5 Direct Media Interface (DMI) Power Management564.6 Graphics Power Management574.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)574.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)574.6.3 Graphics Render C-State574.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)584.6.5 Intel® Graphics Dynamic Frequency584.6.6 Display Power Savings Technology 6.0 (DPST)584.6.7 Automatic Display Brightness (ADB)594.6.8 Intel® Seamless Display Refresh Rate Switching Technology (Intel® SDRRS Technology)594.7 Thermal Power Management595 Thermal Management615.1 Thermal Design Power (TDP) and Junction Temperature (Tj)615.2 Thermal Considerations615.2.1 Intel® Turbo Boost Technology Power Control and Reporting625.2.2 Package Power Control635.2.3 Power Plane Control635.2.4 Turbo Time Parameter635.3 Thermal and Power Specifications645.4 Thermal Management Features675.4.1 Processor Package Thermal Features675.4.1.1 Adaptive Thermal Monitor685.4.1.2 Digital Thermal Sensor705.4.1.3 PROCHOT# Signal715.4.2 Processor Core Specific Thermal Features735.4.2.1 On-Demand Mode735.4.3 Memory Controller Specific Thermal Features735.4.3.1 Programmable Trip Points735.4.4 Platform Environment Control Interface (PECI)745.4.4.1 Fan Speed Control with Digital Thermal Sensor746 Signal Description756.1 System Memory Interface Signals766.2 Memory Reference and Compensation Signals776.3 Reset and Miscellaneous Signals786.4 PCI Express*-Based Interface Signals796.5 Embedded DisplayPort* (eDP) Signals796.6 Intel® Flexible Display Interface (Intel® FDI) Signals806.7 Direct Media Interface (DMI) Signals806.8 Phase Lock Loop (PLL) Signals806.9 Test Access Points (TAP) Signals816.10 Error and Thermal Protection Signals816.11 Power Sequencing Signals826.12 Processor Power Signals826.13 Sense Signals836.14 Ground and Non-Critical to Function (NCTF) Signals836.15 Future Compatibility Signals846.16 Processor Internal Pull-Up / Pull-Down Resistors847 Electrical Specifications857.1 Power and Ground Pins857.2 Decoupling Guidelines857.2.1 Voltage Rail Decoupling857.2.2 PLL Power Supply857.3 Voltage Identification (VID)867.4 System Agent (SA) VCC VID907.5 Reserved or Unused Signals907.6 Signal Groups917.7 Test Access Port (TAP) Connection937.8 Storage Condition Specifications937.9 DC Specifications947.9.1 Voltage and Current Specifications957.10 Platform Environmental Control Interface (PECI) DC Specifications1017.10.1 PECI Bus Architecture1017.10.2 PECI DC Characteristics1027.10.3 Input Device Hysteresis1038 Processor Pin and Signal Information1058.1 Processor Pin Assignments1058.2 Package Mechanical Information1559 DDR Data Swizzling167Size: 3.6 MBPages: 170Language: EnglishOpen manual