Intel i3-2328M FF8062701275100 Data Sheet
Product codes
FF8062701275100
Datasheet, Volume 1
73
Thermal Management
enabled. For more details on the interrupt mechanism, refer to the Intel
®
64 and IA-32
Architectures Software Developer's Manuals.
5.4.2
Processor Core Specific Thermal Features
5.4.2.1
On-Demand Mode
The processor provides an auxiliary mechanism that allows system software to force
the processor to reduce its power consumption using clock modulation. This
mechanism is referred to as “On-Demand” mode and is distinct from Adaptive Thermal
Monitor and bi-directional PROCHOT#. The processor platforms must not rely on
software usage of this mechanism to limit the processor temperature. On-Demand
Mode can be done using processor MSR or chipset I/O emulation.
the processor to reduce its power consumption using clock modulation. This
mechanism is referred to as “On-Demand” mode and is distinct from Adaptive Thermal
Monitor and bi-directional PROCHOT#. The processor platforms must not rely on
software usage of this mechanism to limit the processor temperature. On-Demand
Mode can be done using processor MSR or chipset I/O emulation.
On-Demand Mode may be used in conjunction with the Adaptive Thermal Monitor.
However, if the system software tries to enable On-Demand mode at the same time the
TCC is engaged, the factory configured duty cycle of the TCC will override the duty
cycle selected by the On-Demand mode. If the I/O based and MSR-based On-Demand
modes are in conflict, the duty cycle selected by the I/O emulation-based On-Demand
mode will take precedence over the MSR-based On-Demand Mode.
However, if the system software tries to enable On-Demand mode at the same time the
TCC is engaged, the factory configured duty cycle of the TCC will override the duty
cycle selected by the On-Demand mode. If the I/O based and MSR-based On-Demand
modes are in conflict, the duty cycle selected by the I/O emulation-based On-Demand
mode will take precedence over the MSR-based On-Demand Mode.
5.4.2.1.1
MSR Based On-Demand Mode
If Bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor will
immediately reduce its power consumption using modulation of the internal core clock,
independent of the processor temperature. The duty cycle of the clock modulation is
programmable using Bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In this
mode, the duty cycle can be programmed in either 12.5% or 6.25% increments
(discoverable using CPU ID). Thermal throttling using this method will modulate each
processor core’s clock independently.
immediately reduce its power consumption using modulation of the internal core clock,
independent of the processor temperature. The duty cycle of the clock modulation is
programmable using Bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In this
mode, the duty cycle can be programmed in either 12.5% or 6.25% increments
(discoverable using CPU ID). Thermal throttling using this method will modulate each
processor core’s clock independently.
5.4.2.1.2
I/O Emulation-Based On-Demand Mode
I/O emulation-based clock modulation provides legacy support for operating system
software that initiates clock modulation through I/O writes to ACPI defined processor
clock control registers on the chipset (PROC_CNT). Thermal throttling using this
method will modulate all processor cores simultaneously.
software that initiates clock modulation through I/O writes to ACPI defined processor
clock control registers on the chipset (PROC_CNT). Thermal throttling using this
method will modulate all processor cores simultaneously.
5.4.3
Memory Controller Specific Thermal Features
The memory controller provides the ability to initiate memory throttling based upon
memory temperature. The memory temperature can be provided to the memory
controller using PECI or can be estimated by the memory controller based upon
memory activity. The temperature trigger points are programmable by memory
mapped IO registers.
memory temperature. The memory temperature can be provided to the memory
controller using PECI or can be estimated by the memory controller based upon
memory activity. The temperature trigger points are programmable by memory
mapped IO registers.
5.4.3.1
Programmable Trip Points
This memory controller provides programmable critical, hot and warm trip points.
Crossing a critical trip point forces a system shutdown. Crossing a hot or warm trip
point will initiate throttling. The amount of memory throttle at each trip point is
programmable.
Crossing a critical trip point forces a system shutdown. Crossing a hot or warm trip
point will initiate throttling. The amount of memory throttle at each trip point is
programmable.