Intel i3-2328M FF8062701275100 Data Sheet

86

Datasheet, Volume 1

The VID specifications for the processor V

CC

 and V

AXG

 are defined by the VR12/IMVP7 

SVID Protocol. The processor

 

uses three signals for the serial voltage identification 

interface to support automatic selection of voltages. 

 specifies the voltage 

level corresponding to the eight bit VID value transmitted over serial VID. A ‘1’ in this 
table refers to a high voltage level and a ‘0’ refers to a low voltage level. If the voltage 
regulation circuit cannot supply the voltage that is requested, the voltage regulator 
must disable itself. See the VR12/IMVP7 SVID Protocol for further details. The VID 
codes will change due to temperature and/or current load changes in order to minimize 
the power of the part. A voltage range is provided in 

set so that one voltage regulator can operate with all supported frequencies.

Individual processor VID values may be set during manufacturing so that two devices 
at the same core frequency may have different default VID settings. This is shown in 
the VID range values in 

. The processor

 

provides the ability to operate while 

transitioning to an adjacent VID and its associated voltage. This will represent a DC 
shift in the loadline. 

Transitions above the maximum specified VID are not permitted. 

step sizes and DC shift ranges. Minimum and maximum voltages must be maintained.

The VR used must be capable of regulating its output to the value defined by the new 
VID values issued. DC specifications for dynamic VID transitions are included in 

. See the VR12/IMVP7 SVID Protocol for further details.