Intel 9560 CM8063101049716 Data Sheet

Product codes
CM8063101049716
Page of 172
Intel
®
 Itanium
® 
Processor 9300 Series and 9500 Series Datasheet
67
Electrical Specifications
2.11.2
Supported Power-up Voltage Sequence for the Intel
®
 
Itanium
®
 Processor 9500 Series
Figure 2-18. Supported Power-up Sequence Timing Requirements for Intel® Itanium® 
Processor 9500 Series
VCCSTBY33
(3.3V)
PROCTYPE
VCCIO
VCCA 
(1.8V)
VCC (12V)
>= 0us
VROUTPUT_ENABLE0
RESET_N
PWRGOOD
VCCCORE[1-4]
VCCUNCORE
SVID
VR_READY
1V
Vstrap
V=hfuse
>0us
SYSCLK 
(133MHz)
> 0us
VR_PROCTYPE
Pulled to 3.3VSM pin on platform
Pulled to Ararat’s internal 3.3V rail on Ararat itself
≥15ms 
>= 0us
svid changes 
to vfuse 
values
svid_vcccore 
may change in 
response to 
power 
manager
VCCVUNCOREREADY
svids change 
to hfuse values
Vhfuse
0.9V
Pwrgd reset can change core VR set
V=vfuse
<=1000ms
>0us
> 0us
> 100ms
> 1 ms
All inputs low prior to VCCIO
<200ms