Intel 9560 CM8063101049716 Data Sheet
Product codes
CM8063101049716
Intel
®
Itanium
®
Processor 9300 Series and 9500 Series Datasheet
69
Electrical Specifications
2.13
Timing Relationship Between RESET_N and SKTID
In the processor, the SKTID pins are time-shared:
SKTID[0] is interpreted as a NodeID bit during cold reset and pwrgood reset. It is
interpreted as the error reset modifier during warm-logic reset if SKTID[0] is asserted.
interpreted as the error reset modifier during warm-logic reset if SKTID[0] is asserted.
SKTID[2] is interpreted as a NodeID bit during cold reset and pwrgood reset, and it is
interpreted as an error input being signaled by the system at all other times (except
during non-cold resets when it is ignored).
interpreted as an error input being signaled by the system at all other times (except
during non-cold resets when it is ignored).
show the timing
relationship between RESET_N and SKTID pins for different reset cases.
The LRGSCLSYS pin is sampled only during the PWRGOOD and cold reset period.
The BOOTMODE[2:0] and FLASHROM_CFG[1:0] pins are sampled during the assertion
of all resets except warm-logic resets.
of all resets except warm-logic resets.
Figure 2-19. Supported Power-down Voltage Sequence Timing Requirements
R E S E T _ N
P W G O O D
V R _ O U T P U T _ E N
( 1 3 3 M H z )
V ID s
V C C C O R E
V C C U N C O R E
V C C A
V C C C A C H E
R E F C L K
V C C IO
t
R E S E T _ N
A s fa s t a s p o s s ib le
A ll s u p p lie s to p o w e r d o w n a s fa s t a s
P o s s ib le a fte r P W R G O O D d e a s s e r tio n
> 1 u s
> 0 u s
V C C A M U S T U N P O W E R A L O N G W IT H V C C IO
t
R E S E T _ N
= 1 0 m s fo r In te l Ita n iu m 9 3 0 0 S e r ie s P r o c e s s o r
= 1 5 m s fo r P o u ls o n -M C P r o c e s s o r
> = 0 u s
A
ll
sign
al
in
puts o
n VCC
IO
plane
ca
n p
owe
r
do
wn
with
VC
CIO
c h a n g e to s a fe V ID