Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

204

Order Number: 330061-002US

Unless the SoC Soft Strap GBE_ALL_DISABLE is “1,” an external EEPROM device must 

be connected to the four-wire Serial Peripheral Interface (SPI) bus interface of the GbE 

controller. The controller provides a 2-MHz (typical) serial clock for the bus. Electrical 

and timing specifications are in 

. EEPROM product recommendations and board design guidelines are given 

in the Intel

 Atom™ Processor C2000 Product Family Platform Design Guide (PDG).

When the LAN Port interface is set to operate in SGMII mode, an external PHY device 

can be accessed by the GbE controller through one of two PHY-management interfaces 

types:

• an MII Management interface where communication is through the read/write MDI 

Control (MDIC) register in MMIO, offset 20h.

• or a two-wire standard-mode I

2

C interface where communication is through the 

read/write SGMII I

2

C Command (I2CCMD) register in MMIO, offset 1028h.

The MII Management interface is described in the subsection titled “Management 

functions” of Clause 22 “Reconciliation Sublayer (RS) and Media Independent Interface 

(MII)” of the IEEE Standard 802.3*-2008. The GbE controller supports the optional 

Clause 45 electrical characteristics described in the specification but it does not support 

the logical extensions of Clause 45.

The SoC has two MDIO/I2C interface ports:

• MDIO0 - associated with LAN Port 0. If it is not configured to be dedicated to LAN 

Port 0, this MDIO can be shared with LAN Ports 1, 2, and 3.

• MDIO1 - associated with LAN Port 1. This MDIO cannot be shared with the other 

LAN Ports.

More is said about sharing in 

For each of these two interface ports, the SoC provides a receiver circuit and an open-

drain driver as the interface to the platform board. Electrically, either the I

2

C or MDIO 

interface can be implemented on the platform board.

Regardless which of the two interface types are used by the design, the following bits 

must both be set for the interface pins to function (see 

):

• I

2

C Enabled - bit 25 of the Extended Device Control (CTRL_EXT) register in MMIO, 

offset 18h

• Destination - bit 31 of the MDC/MDIO Configuration (MDICNFG) register in MMIO, 

offset E04h. Bit 31 is initialized by the value of External MDIO (bit 2) of the LAN 

Port’s EEPROM 

CTRL_EXT and MDICNFG registers exist for LAN Port 0 (MDIO0) and for LAN Port 1 

(MDIO1).