Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

228

Order Number: 330061-002US

After the BIOS initializes the PCI Express Root Ports, during the PCI configuration 

(Configuration Read and Configuration Write transactions), the root ports respond to 

Type 0 Configuration Transactions. A Type 0 Configuration Transaction configures the 

root port (the bridge) and is not forwarded downstream by the bridge (from its primary 

to secondary interface).

Once the root port is configured, the bridge decides whether to respond to subsequent 

Type 1 Configuration Transactions. The bridge compares the specified bus number with 

three configuration registers that were programmed by the configuration initialization 

code to determine whether to claim and forward a Type 1 configuration transaction 

across the bridge. For certain bus numbers in a Type 1 Configuration Transaction, the 

root port converts the transaction to a Type 0 Configuration Transaction and passes the 

transaction downstream through its secondary interface.

For additional details about PCI bridge operation, see the PCI-to-PCI Bridge 

Architecture Specification, Revision 1.2.

The 8-bit I/O Base field and the 8-bit I/O Limit field in the standard PCI Bridge Header 

in Configuration Space define how the root port treats PCI I/O-addressed transactions 

between its primary (Root Complex side) and secondary (downstream link) interfaces.

The I/O Base field and the I/O Limit field are set to indicate that root port only supports 

16-bit addressing for I/O-addressed transactions. The root port decodes the full 32 bits 

of each I/O transaction and only accepts I/O transactions where the address bits 

[31:16] are zero.

The I/O Base and I/O Limit fields establish the starting and ending I/O addresses the 

root port accepts for forwarding. Bits [7:4] of these fields define bits [15:12] for I/O 

transaction addresses for the base and limit addresses. Bits [11:0] for the I/O Base 

address are fixed as zero. Bits [11:0] for the I/O Limit address are fixed as all ones.

Notice the 4-KB granularity of the forwarding range.

Since the PCIe Root Ports only support 16-bit I/O-address transactions, the I/O Base 

Upper 16-Bits field and the I/O Base Limit 16-Bits field are not used.