Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

230

Order Number: 330061-002US

When the Bus Master Enable (BME) bit is set in the Root Port Device PCI Command 

register (PCICMD) of the PCI Standard Header in Configuration Space, all bridge 

transactions are treated in a normal fashion. The bridge (the root port) operates as a 

bus master on the primary interface for memory and I/O transactions forwarded from 

the secondary interface.

When BME is set to zero, memory read, memory write, I/O read and I/O write requests 

made in the upstream direction at the root port secondary interface are blocked. Such 

transactions are handled as Unsupported Requests (UR). For these transactions that 

are non-posted requests, a completion is also sent when a UR status is returned.

When BME is set to zero, upstream Message Signaled Interrupts (MSI) are also blocked 

in that they are actually memory write transactions. This also holds true for requests 

issued by agents using the PCIe message-base mechanism to generate legacy PCI 

interrupts (INTx).

The BME bit state does not affect the ability of the root port to forward or convert 

configuration transactions from the secondary interface to the primary interface.