Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

267

As shown in 

, the EHC memory-mapped I/O space is composed of two sets 

of registers:

• Capability Registers
• Operational  Registers

As a target of memory transactions, the EHC does not support memory transactions 

that are locked. Attempting to access the EHC Memory-Mapped I/O space using locked 

memory transactions results in undefined behavior.

When the USB2 function is in the D3 PCI power state, accesses to the USB2 memory 

range are ignored and result in a master abort. Similarly, if the Memory Space Enable 

(MSE) bit is not set in the Command register in configuration space, the memory range 

is not decoded by the EHC. If the MSE bit is not set, then the EHC does not claim any 

memory accesses for the range specified in the BAR.

USB MMIO Base Address + Offset 000h to 01Fh

These registers specify the limits, restrictions, and capabilities of the EHC.

• Offset 08h: HCCPARAMS

 

- Host Controller Capability Parameters. This register 

provides general mode information that affects the generation of the data structure 

in memory. See 

EHCI Capabilities List

Read Only

Exists at offset 68h in the PCI configuration space.

Periodic Schedule Prefetch Capability

R/W

Supported.

Asynchronous Schedule Prefetch Capability

R/W

Supported.

Asynchronous Schedule Park Capability

Read Only

Not Supported.

Isochronous Scheduling Threshold

R/W

Host software assumes the host controller caches 

an isochronous data structure for an entire frame. 

See the EHCI Specification for details.

Programmable Frame List Flag

Read Only

System software must use a frame list length of 

1024 elements.

64-Bit Addressing Capability

Read Only

Data structures using 64-bit address memory 

pointers.