Intel C2518 FH8065501516710 Data Sheet

Product codes

FH8065501516710

Intel

Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

269

Volume 2—Universal Serial Bus (USB) 2.0—C2000 Product Family

Enhanced Host Controller DMA

14.4

Enhanced Host Controller DMA

Each DMA engine contains enough internal buffering for two maximum-sized bus

transactions.

The EHC uses three sources of USB packets. In priority order for each USB microframe,

these are:

1. USB 2.0 Debug Port
2. EHCI Periodic Schedule DMA Engine
3. EHCI Asynchronous Schedule DMA Engine

The EHC always performs any pending debug port transaction at the beginning of a

microframe, followed by any pending periodic traffic for the current microframe. If time

is left in the microframe, the EHC performs any pending asynchronous traffic until the

end of the microframe (EOF1).

Note:

The debug port traffic is only presented on one port (Port #1) The other ports are idle

during this time.

Table 14-4. Asynchronous Schedule DMA Engine

Engine Name

Asynchronous DMA engine

Purpose

Fetch/Store Bulk and Control transfers in the main memory.

When Active

USB core is enabled, run bit is set and asynchronous schedule is enabled.

Burst Type

Two outstanding requests of 8 times 64 bytes.

Interrupts caused

Interrupts and SMIs are generated as a result of DMA transactions.

Table 14-5. Periodic Schedule DMA Engine