Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

268

Order Number: 330061-002US

USB MMIO Base Address + Offset 020h to 3FFh

These registers are divided into two sets.

1. Registers in the core power well

The first register set is at offset 20h to 3Fh. Unless otherwise noted, the core power 

well registers are reset by the assertion of any of the following:

• Core power well hardware reset
• Software-Controlled Host Controller Reset (HCRESET)
• D3-to-D0  reset

This first MMIO operational register set contains the USB2 Command, Status, and 

Interrupt Enable registers. This register set also contains the registers needed to 

configure and operate the Periodic Schedule and Asynchronous Schedule data 

structures in shared memory. The following are noteworthy:

structure link field to construct a 64-bit address.
This register allows the host software to locate all control data structures within 

the same 4-Gbyte memory segment.

2. Registers in the Suspend (SUS) power well

The second MMIO operational register set is located at offset 60h to the end of the 

implemented register space. These registers are implemented in the SUS power well. 

Unless otherwise noted, the Core power well registers are reset by the assertion of 

either of the following:

• SUS power well hardware reset
• HCRESET

This second set contains the Configure Flag Register, the Status and Control Registers 

for the four USB Ports, and the Debug Port Registers.