Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

273

Section 4 of the Enhanced Host Controller Interface Specification for Universal Serial 

Bus, Revision 1.0 goes into detail on the EHC interrupts and the error conditions that 

cause them. All error conditions that the EHC detects are reported through the EHCI 

Interrupt status bits. Only SoC-specific interrupt and error-reporting behavior is 

documented in this section. To fully comprehend the EHC interrupt and error-reporting 

functionality, read the EHCI Interrupts section of the specification before reading the 

rest of this document.

• Based on the EHC Buffer sizes and buffer management policies, the Data Buffer 

Error never occurs on the SoC.

• Master Abort and Target Abort responses from hub interface on EHC-initiated read 

packets are treated as Fatal Host Errors. The EHC halts when these conditions are 

encountered.

• The EHC asserts the interrupts which are based on the interrupt threshold as soon 

as the status for the last complete transaction in the interrupt interval has been 

posted in the internal write buffers. The requirement in the Enhanced Host 

Controller Interface Specification for Universal Serial Bus, Revision 1.0 (that the 

status is written to memory) is met internally, even though the write is not seen on 

DMI before the interrupt is asserted.

• Since the EHC supports the 1024-element Frame List size, the Frame List Rollover 

interrupt occurs every 1024 milliseconds.

• The EHC delivers interrupts to the CPU via the highly-configurable, SoC interrupt 

router. The software communicates with the interrupt router through the USB 8-bit 

Interrupt Line (ILINE_0) register in Configuration Space.

• The USB interrupt pin to IRQ mapping is platform specific. The SoC is free to 

choose.

• The EHC does not support Message Signaled Interrupts (MSI or MSI-X).
• The EHC does not modify the CERR count on an Interrupt IN when the Do 

Complete-Split execution criteria are not met.

• For complete-split transactions in the Periodic list, the Missed Microframe bit does 

not get set on a control-structure-fetch that fails the late-start test. If subsequent 

accesses to that control structure do not fail the late-start test, then the Missed 

Microframe bit is set and written back.

If a read initiated by the EHC is aborted, the EHC treats the aborted read as a fatal host 

error. The following actions are taken when this occurs:

• The Host System Error status bit is set.
• The DMA engines are halted after completing up to one more transaction on the 

USB interface.

• If enabled (by the Host System Error Enable), then an interrupt is generated.
• If the status is Master Abort, then the Received Master Abort bit in configuration 

space is set.

• If the status is Target Abort, then the Received Target Abort bit in configuration 

space is set.

• If enabled (by the SERR Enable bit in the function configuration space), then the 

Signaled System Error bit in configuration bit is set.