Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

275

The way the EHC behavior relates to other power management states in the system 

(S-States) is summarized in the following list:

• The system is always in the S0 state when the EHC is in the D0 state. However, 

when the EHC is in the D3 state, the system is in any power management state, 

including S0.

• When in D0, the Prefetch-Based Pause (PBP) feature enables dynamic processor 

low-power states to be entered.

• The internal clock generators in the EHC are disabled when entering the S5 state 

(the core power turns off).

• All core well logic is reset in the S5 state.

The controller supports using the Suspend (SUS) power well to properly function in the 

S5 system power management states. In these Sx states, the controller SUS power 

well remains powered to detect wake events, such as port resume or connect/

disconnect events.

A Power Management Event (PME) is generated if the controller is armed to wake the 

system out of Sx back into S0.

Wakes are also a function of on-board VBUS (the voltage that the platform provides to 

USB-port devices along with GND) configurations. If the VBUS remains powered during 

Sx, USB devices generate remote walk-up signaling on the bus to wake the system 

from Sx states.

Upon a wake event from Sx, the host controller needs to be re-enumerated before 

transfers begin. USB devices are able to retain their states if VBUS continues be 

powered at the platform board level.

This product feature allows the Asynchronous Schedule DMA engine to remain in sleep 

mode for an extended period of time when certain other system conditions are met.

The Prefetch-Based Pause (PBP) feature works closely with the EHCI Periodic DMA 

Engine to enable the C2 Pop-up feature to achieve significant C3 residency even when 

the software has not paused or disabled the EHCI periodic schedule. PBP is completely 

hardware autonomous and software transparent.

This power savings is achieved by the prefetching of the periodic schedule with a series 

of back-to-back reads and storing information about future activity in the Host 

Controller, thereby creating long periods of time (up to several milliseconds) where no 

memory accesses (and cache snoops) occur.

To avoid race conditions with drivers that are not aware of this feature, that are 

updating the schedule at any given time, this feature is only enabled once the CPU(s) is 

in C2 or deeper. This guarantees that the data structures in memory are not modified. 

C2 Pop-up allows the USB controller to bring the system to C2 for a short duration and 

then returns the system to C3.