Intel C2518 FH8065501516710 Data Sheet

Product codes
FH8065501516710
Page of 746
Volume 2—Universal Serial Bus (USB) 2.0—C2000 Product Family
Power Management
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
276
Order Number: 330061-002US
14.10.5
EHCI Descriptor Cache
The controller implements Asynchronous Descriptor Caching. Prefetch of the 
Asynchronous Schedule is performed only after CPU has entered the Cx state. When 
the list is empty, the controller DMA is prevented from continuously accessing memory. 
If the entire Asynchronous Schedule is able to be stored within the internal, 2 KB cache 
(2 Kbytes), the Asynchronous Schedule DMA operates out of the cache, having the 
benefits of asynchronous caching.
14.10.6
USB Internal Clock Shut Down
To conserve power, the EHC is able to shutdown parts of its internal clock system when 
certain idle conditions are met. Wake events are still detected during clock shut down.
14.10.7
Memory Latency Tolerance
Under special conditions, the platform dynamically enters deeper power savings states 
when all devices in the platform tolerate an established worst-case delay for access to 
memory. The EHC participates in this power-savings mechanism.