Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

304

Order Number: 330061-002US

The SMT architecture takes into account various usage models as envisioned on the 

SoC-based platforms. The focus of the architecture is to keep the hardware overhead 

low for supporting the various usage models and protocols:

• SMBus ARP Mastering or ARP Target
• Embedded Controller (EC) on the SMBus communicating with the SoC

The SMT has no security requirements.

The SMT currently supports three different timing modes: standard (up to 100 kHz), 

fast-mode (up to 400 kHz), and fast-mode plus (up to 1 MHz). The timing requirements 

for fast-mode and fast-mode plus are found in the I

2

C industry specification.

The following section covers design targets for the various timing modes in various 

operating conditions. The SMT controller does not contain dynamic timing adjustment 

to account for varying bus loads or pull-up resistor selections, thus SMT is designed and 

have default settings to meet the specification in the worst case scenarios. This comes 

at the cost of not having optimal frequency for any given timing mode in nominal 

conditions.

Devices also stretch the clock low thus reducing the frequency. These timing estimates 

are assuming the device is not further impacting the timings.

Standard

90-100 kHz*

Fast Mode

350-400 kHz*

Fast Mode Plus

750-1000 kHz*

*Timing assumes the platform design is within the specification for maximum 

rise time allowed requiring appropriate Rpullup value selection for the given 

capacitive load on the bus.