Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
306
Order Number: 330061-002US
15.4.7.2
Master Descriptor
The master descriptor is a ring buffer of individual descriptors set up by the firmware as
shown in
. The descriptor ring buffer is pointed to by the base (MDBA) and
the size is indicated by the MD Size register (MDS). See register definitions for details.
Individual descriptors have a 64-bit pointer into the data buffer with an expected
transmit and/or receive length programmed in the Control field of the descriptors.
The hardware updates the Status WB field in
. See
for detailed descriptions. The remaining three Dwords are updated by the firmware.
The firmware always leads and points by the FWmHeadPtr (MCTRL.FMHP). The
hardware always points by the HWmTailPtr (MSTS.HMTP).
Figure 15-4. Master Descriptor Ring Buffer
Figure 15-5. Master Descriptor Format
Master Descriptor
Base Address
MD
Size
HWmTailPtr
(HW updates)
FWmHeadPtr
(FW updates)
(FW updates)
Control
Data Pointer
Data Buffer
Control
Data Pointer
Control
Data Pointer
Status WB
Status WB
Status WB
+0
< Byte 0
WRLNTH/ COMMAND
RDLNTH
TGTADDR
R
W
N
A
K
A
K
2
1
0
P
E
C
E
C
I
N
T
R
5
4
3
6
7
+1
2
1
0
5
4
3
6
7
+2
2
1
0
5
4
3
6
7
+3
2
1
0
5
4
3
6
7
S
O
E
C
O
O
L
< Byte 4
< Byte 8
DPTR (lower 32 bits of pointer address)
< Byte 12
31
30
29
28
27
26
25
24
23
22
21
19
20
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
< Bit #
RxBytes
COLRTRY
C
R
C
R
C
C
LT
O
L
P
R
R
C/
W
W
R
L
I
2
C
RETRY
S
C
S
C
S
R
D
LT
O
F
A
A
I
R
R
B
L
K
L
K
TxBytes
DPTR (upper 32 bits of pointer address)