Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

305

The SMT as the initiator provides the hardware for the internal agents inside the SoC to 

send/receive data across the SMBus. Due to the various usage models that SMT 

supports, the hardware support exists for initiating reads/writes from/to external 

devices on SMBus. The SMT has the hardware capability to transport them over SMBus 

physical and report status back to the firmware.

The firmware must ensure the data in the transmit data buffers is arranged in the order 

that it wants to send on the bus, i.e., data pointed to by the Tx data pointer are sent 

first on SMBus, then the next byte, etc.

With respect to the receive buffer, data are written to memory as-is received from the 

SMBus physical, i.e., the first byte received is placed in the lowest address, then the 

next byte, etc.

The hardware implements a 240-byte buffer which it uses to queue transactions (both 

master-transmitter and master-receiver) as a descriptor-based master. The hardware 

supports a maximum read of 240 bytes.

The storage queues are not shared between the master and the target. Both logical 

sides function independently without dependency on each other.

Although SMT theoretically supports master-initiated write and read cycles of arbitrary 

length, the practical expectation is that the transaction size does not exceed 80B.