Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

344

Order Number: 330061-002US

The hardware tracks the following conditions for errors:

1. SMBus clock-low time-out: status is set when the hardware observes the SMBus 

clock asserted low for more than the value programmed by the firmware.

2. SMBus data-low time-out: status is set when the hardware observes the SMBus 

data asserted low for more than the value programmed by the firmware.

3. Target ring buffer almost full: status is set when the hardware detects the target 

ring buffer has less than 85-B free space remaining in the target ring buffer. This 

check is done after the hardware performs a memory write for data/header.

4. Target ring buffer full: status is set when the hardware in unable to evict its internal 

buffer/header WB to memory due to lack of space in the target ring buffer. This 

check is done every time the hardware needs to write to memory.

1. Cause Interrupt Mask: see ERRINTMSKand ERRAERMSK.

2. Cause Interrupt Status: see ERRSTS. 

Cause occurs, but interrupts are 

not enabled

0

0

0  ->  1

No  MSI  sent

MSI enable is set, cause enable 

and cause status are previously 

set

0 -> 1

1

1

Send MSI

MSI enable and cause status 

previously set, cause interrupt 

enable is set

1

0 -> 1

1

Send MSI

Cause status register gets set, 

interrupts are enabled

1

1

0  ->  1

Send  MSI

Cause status register previously 

set, interrupts are enabled, new 

cause occurs

1

1

1  ->  1

Does not occur since if interrupts 

are enabled, Cause Status is 

cleared. If the clearing happens on 

the same clock as the new cause is 

set, it is the rule in the next row 

before.

New cause occurs in the same 

clock as the previous MSI 

scheduled was sent

1

1

1  ->  1

Send  MSI

Scheduled MSI was sent

1

1

1 -> 0

The hardware auto-clears the 

cause register.

MSI is scheduled to be sent when 

MSI enable is cleared

1 -> 0

1

0 -> 1 

or

1 -> 1

The hardware schedules the MSI or 

drops it.
Any pending MSIs must be 

reflected in the MSI Pending 

Register.