Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
345
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Interrupts
15.5.4
Interrupt Cause Logging
Before sending any MSI, the hardware writes information pertinent to the interrupt
.
As indicated in
, the Dwords of SMTICL are divided into three categories.
The hardware updates only the relevant Dword depending on the nature of the
interrupt: interrupts generated during a master transaction involves updates only to
Dword #0; likewise target transactions involve only Dword #1. However, if an error
condition is present, the hardware requires also writing to Dword #2 to capture the
nature of the error.
The firmware always reads all three Dwords, and upon reading them clears any Dword
which has non-zero data. (At a minimum two Dwords must be read—master + error or
target + error.)
Table 15-23. Interrupt Cause Information
Dword Bit
Field
Description
Information from MASTER
0
31
MSTR.VALID
Master interrupt cause is valid
1: denotes master status (MSTS), including the master hardware
1: denotes master status (MSTS), including the master hardware
tail pointer, has been written
0
30:0
Reserved
Information from TARGET
1
31
TRGT.VALID
Target interrupt cause is valid
1: denotes the target hardware head pointer (HTHP) has been
1: denotes the target hardware head pointer (HTHP) has been
written
1
30:0
Reserved
Error Information
2
31
ERR.VALID
Error interrupt cause is valid
1: denotes errors status (ERRSTS) has been written
1: denotes errors status (ERRSTS) has been written
2
30:0
Reserved