Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

365

0

+ 0h

21

VDDQ Channel 1

Enable

Channel 1 DRAM SVID VDDQ Voltage Enabled
1'b0 (false) - Disabled (No SVID Support)
1'b1 (true) - Enabled (With SVID Support)

1. SVID based VR on VDDQ0 and SVID based VR on VDDQ1

• Soft straps should be set to VDDQ CH0 : 1 , VDDQ CH1 : 1

2. Single SVID Based VR for both VDDQ0 and VDDQ1:

• Soft straps should be set to VDDQ CH0 : 1 , VDDQ CH1 : 0

3. No SVID based VR for both VDDQ0 and VDDQ1:

• Soft straps should be set to VDDQ CH0 : 0 , VDDQ CH1 : 0

1'b1

0

+ 0h

26:22

Reserved

Reserved

5'h0

0

+ 0h

27

No Reboot

Platform Reset (PMU_PLTRST_B ) after TCO WDT second time 

expiration Disabled:
1'b0 (false) - Enabled
1'b1 (true) - Disabled

1'b0

0

+ 0h

31:28

Reserved

Reserved

4'h0

1

+ 4h

3:0

Reserved

Reserved

N/A

1

+ 4h

4

COREPWROK_Wait

Wait Forever for Core Power OK (COREPWROK) assertion:
1’b0 - Watch Dog Timer (WDT) expiration will cause an SoC 

reset
1’b1 -WDT will not cause an SoCSoC reset while waiting for 

Core Pwr OK 

1’b0

1

+ 4h

31:5

Reserved

Reserved

N/A

2

+ 8h

4:0

Reserved

Reserved

5'h0

2

+ 8h

17:5

BIOS Protected 

Range 4 Base

Specifies the lower base of the BIOS protected range number 4. 

Address bits [11:0] are assumed to be 12'h000 for the base 

comparison. [Goes to bits [12:0] at register: 

[Protected_Range_4] PR4 (at 0x84)]

13'h0

2

+ 8h

30:18

BIOS Protected 

Range 4 Limit

Specifies the upper limit of the BIOS protected range number 4. 

Address bits [11:0] are assumed to be 12'hFFF for the limit 

comparison. [Goes to bits [28:16] at register: 

[Protected_Range_4] PR4 (at 0x84)]

13'h0

2

+ 8h

31

BIOS PR4 Write 

Protection Enable

When set (true), this bit indicates that the base and limit fields 

are valid and that writes directed to the addresses between 

them (inclusive) must be blocked by the hardware. The base 

and limit fields are ignored when this bit is cleared. Disabling 

this protected range is done also by the security override pin 

strap. [This soft strap and the security override pin strap are 

reflected into bit 31 at register: [Protected_Range_4] PR4 (at 

0x84).]

1'b0

3

+ 0Ch

1:0

Reserved

Reserved

2’b00

3

+ 0Ch

9:2

8 bit OEM Scratch 

Pad

8 bit OEM Scratch Pad. An example usage would to be to store 

system memory down information.

8’h0

3

+ 0Ch

31:10

Reserved

Reserved

22’h0

4

+ 10h

31:0

Reserved

Reserved

N/A