Intel C2518 FH8065501516710 Data Sheet
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Product codes
FH8065501516710
Volume 2—Platform Controller Unit (PCU)—C2000 Product Family
Soft Straps
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
366
Order Number: 330061-002US
5
+ 14h
5:0
Reserved
Reserved
6’h0
5
+ 14h
6
PCIe RP1, 2, 3 or 4
Enabled
PCIe Root Ports 1, 2, 3, or 4 are Enabled:
1'b0 (false) - All are Disabled.
1'b1 (true) - At least 1 is Enabled.
1'b0 (false) - All are Disabled.
1'b1 (true) - At least 1 is Enabled.
Note:
Ensure these soft straps are set to match this selection.
• SoC Strap 0 PCIe RP1 Disable
• SoC Strap 0 PCIe RP2 Disable
• SoC Strap 0 PCIe RP3 Disable
• SoC Strap 0 PCIe RP4 Disable
• SoC Strap 0 PCIe RP2 Disable
• SoC Strap 0 PCIe RP3 Disable
• SoC Strap 0 PCIe RP4 Disable
1'b1
5
+ 14h
7
PCIe Power Enabled
Lane 0
PCIe Power Enabled Lane 0:
1'b0 (false) - Disabled
1'b1 (true) - Enabled
1'b0 (false) - Disabled
1'b1 (true) - Enabled
Note:
Disable this lane if disabling PCIe RP1.
1'b1
5
+ 14h
8
PCIe Power Enabled
Lane 1
PCIe Power Enabled Lane 1:
1'b0 (false) - Disabled
1'b1 (true) - Enabled
1'b0 (false) - Disabled
1'b1 (true) - Enabled
Note:
Disable this lane if disabling PCIe RP1.
1'b1
5
+ 14h
9
PCIe Power Enabled
Lane 2
PCIe Power Enabled Lane 2:
1'b0 (false) - Disabled
1'b1 (true) - Enabled
1'b0 (false) - Disabled
1'b1 (true) - Enabled
Note:
Disable this lane if disabling PCIe RP1.
1'b1
5
+ 14h
10
PCIe Power Enabled
Lane 3
PCIe Power Enabled Lane 3:
1'b0 (false) - Disabled
1'b1 (true) - Enabled
1'b0 (false) - Disabled
1'b1 (true) - Enabled
Note:
Disable this lane if disabling PCIe RP1.
1'b1
5
+ 14h
11
PCIe Power Enabled
Lane 4
PCIe Power Enabled Lane 4:
1'b0 (false) - Disabled
1'b1 (true) - Enabled
1'b0 (false) - Disabled
1'b1 (true) - Enabled
Note:
Disable this lane if disabling PCIe RP1 and PCIe RP2.
1'b1
5
+ 14h
12
PCIe Power Enabled
Lane 5
PCIe Power Enabled Lane 5:
1'b0 (false) - Disabled
1'b1 (true) - Enabled
1'b0 (false) - Disabled
1'b1 (true) - Enabled
Note:
Disable this lane if disabling PCIe RP1 and PCIe RP2.
1'b1
5
+ 14h
13
PCIe Power Enabled
Lane 6
PCIe Power Enabled Lane 6:
1'b0 (false) - Disabled
1'b1 (true) - Enabled
1'b0 (false) - Disabled
1'b1 (true) - Enabled
Note:
Disable this lane if disabling PCIe RP1 and PCIe RP2.
1'b1
5
+ 14h
14
PCIe Power Enabled
Lane 7
PCIe Power Enabled Lane 7:
1'b0 (false) - Disabled
1'b1 (true) - Enabled
1'b0 (false) - Disabled
1'b1 (true) - Enabled
Note:
Disable this lane if disabling PCIe RP1 and PCIe RP2.
1'b1
Table 16-5. Flash Descriptor Soft Strap (Sheet 5 of 10)
FITC
SoC
Strap
Number
FISBA
+
Offset
Bit
Offset
Soft Strap Name
Description
Default