Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

437

The SoC, as a SMBus master, drives the clock. When the SoC is sending an address or 

a command or data bytes on writes, it drives the data relative to the clock it is also 

driving. It does not start toggling the clock until the start or stop condition meets the 

proper setup and hold time. The SoC also ensures minimum time between the SMBus 

transactions as a master.

Some devices are not able to handle their clock toggling at the rate that the SoC as an 

SMBus master is currently. They can stretch the low time of the clock. When the SoC 

attempts to release the clock (allowing the clock to go high), the clock remains low for 

an extended period of time.

The SoC monitors the SMBus clock line after it releases the bus to determine whether 

to enable the counter for the high time of the clock. While the bus is still low, the high 

time counter must not be enabled. Similarly, the low period of the clock is stretched by 

an SMBus master if it is not ready to send or receive data.

The 25 ms time-out counter does not count under the following conditions:

1. The SMB_Mem_HSTS.BYTE_DONE_STS bit is set.
2. The TCO_STS.SECOND_TO_STS bit is not set (this indicates that the system has