Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—SMBus 2.0 Unit 0 - PCU—C2000 Product Family
System Host Controller
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
438
Order Number: 330061-002US
18.3.4
Interrupts and SMI
specify how the various enable bits in the SMBus function
control the generation of the interrupt, host SMI, and wake internal signals. The rows in
the tables are additive, which means that if more than one row is true for a particular
scenario then the results for all of the activated rows occur.
18.3.5
SMBALRT_N
Note:
Using this signal as a wake event from S5 is not supported.
Table 18-4. Enable for SMBALRT_N
Event
INTREN
Result
X
1
0
Slave SMI
generated
(SMBUS_SMI_STS)
1
0
0
Interrupt
generated
Table 18-5. Enables for SMBus Host Events
Event
INTREN
Event
0
X
None
1
0
Interrupt generated
1
1
Host SMI generated
Table 18-6. Enables for the Host Notify Command
Result
0
X
0
None
1
0
X
Interrupt generated
1
1
X
Slave SMI generated
(SMBUS_SMI_STS)