Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

473

Communication on the SPI bus is done with a master–slave protocol. See 

 

for the master-slave connection of the SPI devices. Communication is full duplex in that 

data is transferred out at the same time it is transferred into a device. The Slave 

Output (SO) data is implemented through a tri-state bus. No SPI industry standard 

exists, but the communication is similar to the SMBus.

The SoC can boot the system BIOS and the system firmware through the Low Pin-

Count (LPC) bus or through the SPI. The SoC detects from the hard straps which of 

these two BIOS/firmware boot sources to use. This is described further in 

). This is also true in platforms that implement and strap the LPC as the 

boot source. Here the LPC device contains the boot code, but the soft-strap information 

is on the SPI memory device.

SPI Flash Memory 

Device

(SPI Slave)

CS#

CLK

SI

SO

SPI Flash Memory 

Device

(SPI Slave)

CS#

CLK

SI

SO

SPI Controller

(SPI Master)

SPI_MOSI

SPI_CS0_B

SPI_CS1_B

SPI_CLK

SPI_MISO