Intel C2518 FH8065501516710 Data Sheet

Product codes
FH8065501516710
Page of 746
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
475
Volume 2—Serial Peripheral Interface (SPI)—C2000 Product Family
Operation Modes
22.4.2
Descriptor Mode
The descriptor mode is required to enable many features:
• Secure Boot
• PCI Express* Root Port configuration
• Support for two SPI components using two separate chip-select pins
• Hardware-enforced security restricting master accesses to different regions
• Soft-strap region providing the ability to use Flash Non-Volatile Memory (NVM) to 
remove the need for pull-up/pull-down resistors for hard-strapping SoC features
• Support for the SPI fast read instruction and frequencies greater than 20 MHz
• Support for single-input, dual-output fast reads
• Use of standardized Flash instruction set
22.4.2.1
SPI Flash Regions
In the descriptor mode, the Flash is divided into five separate regions as shown in 
.
Only the CPU core running the BIOS code accesses the SPI Flash regions. The only 
required region is region 0, the Flash Descriptor. Region 0 must be located in the first 
sector of device 0. 
22.4.2.2
Flash Regions Sizes
The SPI Flash space requirements differ by platform and configuration. 
 
indicates the amount of memory needed in the Flash device for each region.
Table 22-3. SPI Flash Regions
Region
Content
Comment
0
Flash Descriptor
1
BIOS
2
Security Engine
Not Supported
3
Integrated Gigabit Ethernet
Reserved 
4
Platform Data
Table 22-4. Region Size Versus Erase Granularity of Flash Components
Region
Size with 4-KB
Erase Blocks
Size with 8-KB
Erase Blocks
Size with 64-KB
Erase Blocks
Flash Descriptor Region
4 KB
4 KB
4 KB
BIOS Region
Varies by Platform
Varies by Platform
Varies by Platform